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git01.mediatek.com / filogic / atf / 537bce44d3aecf78b272f54459f15b43d689ff06 / . / plat / nvidia / tegra / soc / t194 / drivers / include / mce_private.h
blob: 473540473be583b9c66970e69af4de541fc09558 [file] [log] [blame]
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]1/*
2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __MCE_PRIVATE_H__
8#define __MCE_PRIVATE_H__
9
10#include <mmio.h>
11#include <tegra_def.h>
12
13/*******************************************************************************
14 * Macros to prepare CSTATE info request
15 ******************************************************************************/
16/* Description of the parameters for UPDATE_CSTATE_INFO request */
17#define CLUSTER_CSTATE_MASK 0x7
18#define CLUSTER_CSTATE_SHIFT 0
19#define CLUSTER_CSTATE_UPDATE_BIT (1 << 7)
20#define CCPLEX_CSTATE_MASK 0x3
21#define CCPLEX_CSTATE_SHIFT 8
22#define CCPLEX_CSTATE_UPDATE_BIT (1 << 15)
23#define SYSTEM_CSTATE_MASK 0xF
24#define SYSTEM_CSTATE_SHIFT 16
25#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22
26#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1 << 22)
27#define SYSTEM_CSTATE_UPDATE_BIT (1 << 23)
28#define CSTATE_WAKE_MASK_UPDATE_BIT (1 << 31)
29#define CSTATE_WAKE_MASK_SHIFT 32
30#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFF
31
32/*******************************************************************************
33 * Auto-CC3 control macros
34 ******************************************************************************/
35#define MCE_AUTO_CC3_FREQ_MASK 0x1FF
36#define MCE_AUTO_CC3_FREQ_SHIFT 0
37#define MCE_AUTO_CC3_VTG_MASK 0x7F
38#define MCE_AUTO_CC3_VTG_SHIFT 16
39#define MCE_AUTO_CC3_ENABLE_BIT (1 << 31)
40
41/*******************************************************************************
42 * Macros for the 'IS_SC7_ALLOWED' command
43 ******************************************************************************/
44#define MCE_SC7_ALLOWED_MASK 0x7
45#define MCE_SC7_WAKE_TIME_SHIFT 32
46
47/*******************************************************************************
48 * Macros for 'read/write ctats' commands
49 ******************************************************************************/
50#define MCE_CSTATE_STATS_TYPE_SHIFT 32
51#define MCE_CSTATE_WRITE_DATA_LO_MASK 0xF
52
53/*******************************************************************************
54 * Macros for 'update crossover threshold' command
55 ******************************************************************************/
56#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32
57
58/*******************************************************************************
59 * Timeout value used to powerdown a core
60 ******************************************************************************/
61#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF
62
63/*******************************************************************************
64 * MCA command struct
65 ******************************************************************************/
66typedef union mca_cmd {
67 struct command {
68 uint8_t cmd;
69 uint8_t idx;
70 uint8_t subidx;
71 } command;
72 struct input {
73 uint32_t low;
74 uint32_t high;
75 } input;
76 uint64_t data;
77} mca_cmd_t;
78
79/*******************************************************************************
80 * MCA argument struct
81 ******************************************************************************/
82typedef union mca_arg {
83 struct err {
84 uint64_t error:8;
85 uint64_t unused:48;
86 uint64_t finish:8;
87 } err;
88 struct arg {
89 uint32_t low;
90 uint32_t high;
91 } arg;
92 uint64_t data;
93} mca_arg_t;
94
95/*******************************************************************************
96 * Uncore PERFMON ARI struct
97 ******************************************************************************/
98typedef union uncore_perfmon_req {
99 struct perfmon_command {
100 /*
101 * Commands: 0 = READ, 1 = WRITE
102 */
103 uint64_t cmd:8;
104 /*
105 * The unit group: L2=0, L3=1, ROC=2, MC=3, IOB=4
106 */
107 uint64_t grp:4;
108 /*
109 * Unit selector: Selects the unit instance, with 0 = Unit
110 * = (number of units in group) - 1.
111 */
112 uint64_t unit:4;
113 /*
114 * Selects the uncore perfmon register to access
115 */
116 uint64_t reg:8;
117 /*
118 * Counter number. Selects which counter to use for
119 * registers NV_PMEVCNTR and NV_PMEVTYPER.
120 */
121 uint64_t counter:8;
122 } perfmon_command;
123 struct perfmon_status {
124 /*
125 * Resulting command status
126 */
127 uint64_t val:8;
128 uint64_t unused:24;
129 } perfmon_status;
130 uint64_t data;
131} uncore_perfmon_req_t;
132
133#define UNCORE_PERFMON_CMD_READ 0
134#define UNCORE_PERFMON_CMD_WRITE 1
135
136#define UNCORE_PERFMON_CMD_MASK 0xFF
137#define UNCORE_PERFMON_UNIT_GRP_MASK 0xF
138#define UNCORE_PERFMON_SELECTOR_MASK 0xF
139#define UNCORE_PERFMON_REG_MASK 0xFF
140#define UNCORE_PERFMON_CTR_MASK 0xFF
141#define UNCORE_PERFMON_RESP_STATUS_MASK 0xFF
142
143/* declarations for NVG handler functions */
144int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
145int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
146 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
147 uint8_t update_wake_mask);
148int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time);
149uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state);
150int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t val);
151int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
152int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
153int nvg_online_core(uint32_t ari_base, uint32_t core);
154int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
155
156#endif /* __MCE_PRIVATE_H__ */