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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
Julius Werner65d52672019-05-24 20:37:58 -07002 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
Tony Xief6118cc2016-01-15 17:17:32 +08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +08005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef PLAT_PRIVATE_H
8#define PLAT_PRIVATE_H
Tony Xief6118cc2016-01-15 17:17:32 +08009
10#ifndef __ASSEMBLY__
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
Tony Xief6118cc2016-01-15 17:17:32 +080012#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013
14#include <lib/psci/psci.h>
15#include <lib/xlat_tables/xlat_tables.h>
16#include <lib/mmio.h>
Julius Werner65d52672019-05-24 20:37:58 -070017#include <plat_params.h>
Tony Xief6118cc2016-01-15 17:17:32 +080018
Caesar Wangd90f43e2016-10-11 09:36:00 +080019#define __sramdata __attribute__((section(".sram.data")))
20#define __sramconst __attribute__((section(".sram.rodata")))
Lin Huang30e43392017-05-04 16:02:45 +080021#define __sramfunc __attribute__((section(".sram.text")))
22
23#define __pmusramdata __attribute__((section(".pmusram.data")))
24#define __pmusramconst __attribute__((section(".pmusram.rodata")))
25#define __pmusramfunc __attribute__((section(".pmusram.text")))
Caesar Wangd90f43e2016-10-11 09:36:00 +080026
27extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
28extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
Lin Huang30e43392017-05-04 16:02:45 +080029extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end;
Lin Huang88dd1232017-05-16 16:40:46 +080030extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end;
Xing Zheng93280b72016-10-26 21:25:26 +080031extern uint32_t __sram_incbin_start, __sram_incbin_end;
Lin Huang88dd1232017-05-16 16:40:46 +080032extern uint32_t __sram_incbin_real_end;
Caesar Wangd90f43e2016-10-11 09:36:00 +080033
Tony Xief6118cc2016-01-15 17:17:32 +080034/******************************************************************************
35 * The register have write-mask bits, it is mean, if you want to set the bits,
36 * you needs set the write-mask bits at the same time,
37 * The write-mask bits is in high 16-bits.
38 * The fllowing macro definition helps access write-mask bits reg efficient!
39 ******************************************************************************/
40#define REG_MSK_SHIFT 16
41
Tony Xief6118cc2016-01-15 17:17:32 +080042#ifndef WMSK_BIT
43#define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT)
44#endif
45
46/* set one bit with write mask */
47#ifndef BIT_WITH_WMSK
48#define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr))
49#endif
50
51#ifndef BITS_SHIFT
52#define BITS_SHIFT(bits, shift) (bits << (shift))
53#endif
54
55#ifndef BITS_WITH_WMASK
Caesar Wang59e41b52016-04-10 14:11:07 +080056#define BITS_WITH_WMASK(bits, msk, shift)\
Tony Xief6118cc2016-01-15 17:17:32 +080057 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
58#endif
59
60/******************************************************************************
61 * Function and variable prototypes
62 *****************************************************************************/
Heiko Stuebner9dc28332019-03-14 22:11:34 +010063#ifdef AARCH32
64void plat_configure_mmu_svc_mon(unsigned long total_base,
65 unsigned long total_size,
66 unsigned long,
67 unsigned long,
68 unsigned long,
69 unsigned long);
70
71void rockchip_plat_mmu_svc_mon(void);
72#else
Tony Xief6118cc2016-01-15 17:17:32 +080073void plat_configure_mmu_el3(unsigned long total_base,
74 unsigned long total_size,
75 unsigned long,
76 unsigned long,
77 unsigned long,
78 unsigned long);
79
Heiko Stuebner9dc28332019-03-14 22:11:34 +010080void rockchip_plat_mmu_el3(void);
81#endif
82
Tony Xief6118cc2016-01-15 17:17:32 +080083void plat_cci_init(void);
84void plat_cci_enable(void);
85void plat_cci_disable(void);
86
87void plat_delay_timer_init(void);
88
Julius Werner65d52672019-05-24 20:37:58 -070089void params_early_setup(u_register_t plat_params_from_bl2);
Caesar Wang3e3c5b02016-05-25 19:03:04 +080090
Tony Xief6118cc2016-01-15 17:17:32 +080091void plat_rockchip_gic_driver_init(void);
92void plat_rockchip_gic_init(void);
93void plat_rockchip_gic_cpuif_enable(void);
94void plat_rockchip_gic_cpuif_disable(void);
95void plat_rockchip_gic_pcpu_init(void);
96
Tony Xief6118cc2016-01-15 17:17:32 +080097void plat_rockchip_pmu_init(void);
98void plat_rockchip_soc_init(void);
Tony Xie42e113e2016-07-16 11:16:51 +080099uintptr_t plat_get_sec_entrypoint(void);
Tony Xief6118cc2016-01-15 17:17:32 +0800100
Caesar Wang59e41b52016-04-10 14:11:07 +0800101void platform_cpu_warmboot(void);
102
Julius Werner65d52672019-05-24 20:37:58 -0700103struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void);
104struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void);
105struct bl_aux_gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
106struct bl_aux_rk_apio_info *plat_get_rockchip_suspend_apio(void);
Caesar Wang038f6aa2016-05-25 19:21:43 +0800107void plat_rockchip_gpio_init(void);
Lin Huang2c60b5f2017-05-18 18:04:25 +0800108void plat_rockchip_save_gpio(void);
109void plat_rockchip_restore_gpio(void);
Caesar Wang038f6aa2016-05-25 19:21:43 +0800110
tony.xie422d51c2017-03-01 11:05:17 +0800111int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint);
112int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
113 plat_local_state_t lvl_state);
114int rockchip_soc_cores_pwr_dm_off(void);
115int rockchip_soc_sys_pwr_dm_suspend(void);
116int rockchip_soc_cores_pwr_dm_suspend(void);
117int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
118 plat_local_state_t lvl_state);
119int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
120 plat_local_state_t lvl_state);
121int rockchip_soc_cores_pwr_dm_on_finish(void);
122int rockchip_soc_sys_pwr_dm_resume(void);
123
124int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
125 plat_local_state_t lvl_state);
126int rockchip_soc_cores_pwr_dm_resume(void);
127void __dead2 rockchip_soc_soft_reset(void);
128void __dead2 rockchip_soc_system_off(void);
129void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(
130 const psci_power_state_t *target_state);
131void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void);
132
Tony Xief6118cc2016-01-15 17:17:32 +0800133extern const unsigned char rockchip_power_domain_tree_desc[];
134
Lin Huang30e43392017-05-04 16:02:45 +0800135extern void *pmu_cpuson_entrypoint;
Heiko Stuebner9dc28332019-03-14 22:11:34 +0100136extern u_register_t cpuson_entry_point[PLATFORM_CORE_COUNT];
Tony Xief6118cc2016-01-15 17:17:32 +0800137extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT];
138
139extern const mmap_region_t plat_rk_mmap[];
Caesar Wangd90f43e2016-10-11 09:36:00 +0800140
Christoph Müllnercb9204a2019-04-19 14:16:27 +0200141uint32_t rockchip_get_uart_base(void);
142
Tony Xief6118cc2016-01-15 17:17:32 +0800143#endif /* __ASSEMBLY__ */
144
Tony Xie42e113e2016-07-16 11:16:51 +0800145/******************************************************************************
146 * cpu up status
147 * The bits of macro value is not more than 12 bits for cmp instruction!
148 ******************************************************************************/
149#define PMU_CPU_HOTPLUG 0xf00
150#define PMU_CPU_AUTO_PWRDN 0xf0
151#define PMU_CLST_RET 0xa5
Tony Xief6118cc2016-01-15 17:17:32 +0800152
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000153#endif /* PLAT_PRIVATE_H */