Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PMU_H__ |
| 32 | #define __PMU_H__ |
| 33 | |
Caesar Wang | 0620bb8 | 2016-10-27 01:10:28 +0800 | [diff] [blame] | 34 | #include <pmu_regs.h> |
| 35 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 36 | /* Allocate sp reginon in pmusram */ |
| 37 | #define PSRAM_SP_SIZE 0x80 |
| 38 | #define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE) |
| 39 | |
| 40 | /***************************************************************************** |
| 41 | * Common define for per soc pmu.h |
| 42 | *****************************************************************************/ |
| 43 | /* The ways of cores power domain contorlling */ |
| 44 | enum cores_pm_ctr_mode { |
| 45 | core_pwr_pd = 0, |
| 46 | core_pwr_wfi = 1, |
| 47 | core_pwr_wfi_int = 2 |
| 48 | }; |
| 49 | |
| 50 | /***************************************************************************** |
| 51 | * pmu con,reg |
| 52 | *****************************************************************************/ |
| 53 | #define PMU_WKUP_CFG(n) ((n) * 4) |
| 54 | |
| 55 | #define PMU_CORE_PM_CON(cpu) (0xc0 + (cpu * 4)) |
| 56 | |
| 57 | /* the shift of bits for cores status */ |
| 58 | enum pmu_core_pwrst_shift { |
| 59 | clstl_cpu_wfe = 2, |
| 60 | clstl_cpu_wfi = 6, |
| 61 | clstb_cpu_wfe = 12, |
| 62 | clstb_cpu_wfi = 16 |
| 63 | }; |
| 64 | |
| 65 | #define CKECK_WFE_MSK 0x1 |
| 66 | #define CKECK_WFI_MSK 0x10 |
| 67 | #define CKECK_WFEI_MSK 0x11 |
| 68 | |
| 69 | enum pmu_powerdomain_id { |
| 70 | PD_CPUL0 = 0, |
| 71 | PD_CPUL1, |
| 72 | PD_CPUL2, |
| 73 | PD_CPUL3, |
| 74 | PD_CPUB0, |
| 75 | PD_CPUB1, |
| 76 | PD_SCUL, |
| 77 | PD_SCUB, |
| 78 | PD_TCPD0, |
| 79 | PD_TCPD1, |
| 80 | PD_CCI, |
| 81 | PD_PERILP, |
| 82 | PD_PERIHP, |
| 83 | PD_CENTER, |
| 84 | PD_VIO, |
| 85 | PD_GPU, |
| 86 | PD_VCODEC, |
| 87 | PD_VDU, |
| 88 | PD_RGA, |
| 89 | PD_IEP, |
| 90 | PD_VO, |
| 91 | PD_ISP0 = 22, |
| 92 | PD_ISP1, |
| 93 | PD_HDCP, |
| 94 | PD_GMAC, |
| 95 | PD_EMMC, |
| 96 | PD_USB3, |
| 97 | PD_EDP, |
| 98 | PD_GIC, |
| 99 | PD_SD, |
| 100 | PD_SDIOAUDIO, |
| 101 | PD_END |
| 102 | }; |
| 103 | |
| 104 | enum powerdomain_state { |
| 105 | PMU_POWER_ON = 0, |
| 106 | PMU_POWER_OFF, |
| 107 | }; |
| 108 | |
| 109 | enum pmu_bus_id { |
| 110 | BUS_ID_GPU = 0, |
| 111 | BUS_ID_PERILP, |
| 112 | BUS_ID_PERIHP, |
| 113 | BUS_ID_VCODEC, |
| 114 | BUS_ID_VDU, |
| 115 | BUS_ID_RGA, |
| 116 | BUS_ID_IEP, |
| 117 | BUS_ID_VOPB, |
| 118 | BUS_ID_VOPL, |
| 119 | BUS_ID_ISP0, |
| 120 | BUS_ID_ISP1, |
| 121 | BUS_ID_HDCP, |
| 122 | BUS_ID_USB3, |
| 123 | BUS_ID_PERILPM0, |
| 124 | BUS_ID_CENTER, |
| 125 | BUS_ID_CCIM0, |
| 126 | BUS_ID_CCIM1, |
| 127 | BUS_ID_VIO, |
| 128 | BUS_ID_MSCH0, |
| 129 | BUS_ID_MSCH1, |
| 130 | BUS_ID_ALIVE, |
| 131 | BUS_ID_PMU, |
| 132 | BUS_ID_EDP, |
| 133 | BUS_ID_GMAC, |
| 134 | BUS_ID_EMMC, |
| 135 | BUS_ID_CENTER1, |
| 136 | BUS_ID_PMUM0, |
| 137 | BUS_ID_GIC, |
| 138 | BUS_ID_SD, |
| 139 | BUS_ID_SDIOAUDIO, |
| 140 | }; |
| 141 | |
| 142 | enum pmu_bus_state { |
| 143 | BUS_ACTIVE, |
| 144 | BUS_IDLE, |
| 145 | }; |
| 146 | |
| 147 | /* pmu_cpuapm bit */ |
| 148 | enum pmu_cores_pm_by_wfi { |
| 149 | core_pm_en = 0, |
| 150 | core_pm_int_wakeup_en, |
| 151 | core_pm_resv, |
| 152 | core_pm_sft_wakeup_en |
| 153 | }; |
| 154 | |
| 155 | enum pmu_wkup_cfg0 { |
| 156 | PMU_GPIO0A_POSE_WKUP_EN = 0, |
| 157 | PMU_GPIO0B_POSE_WKUP_EN = 8, |
| 158 | PMU_GPIO0C_POSE_WKUP_EN = 16, |
| 159 | PMU_GPIO0D_POSE_WKUP_EN = 24, |
| 160 | }; |
| 161 | |
| 162 | enum pmu_wkup_cfg1 { |
| 163 | PMU_GPIO0A_NEGEDGE_WKUP_EN = 0, |
| 164 | PMU_GPIO0B_NEGEDGE_WKUP_EN = 7, |
| 165 | PMU_GPIO0C_NEGEDGE_WKUP_EN = 16, |
| 166 | PMU_GPIO0D_NEGEDGE_WKUP_EN = 24, |
| 167 | }; |
| 168 | |
| 169 | enum pmu_wkup_cfg2 { |
| 170 | PMU_GPIO1A_POSE_WKUP_EN = 0, |
| 171 | PMU_GPIO1B_POSE_WKUP_EN = 7, |
| 172 | PMU_GPIO1C_POSE_WKUP_EN = 16, |
| 173 | PMU_GPIO1D_POSE_WKUP_EN = 24, |
| 174 | }; |
| 175 | |
| 176 | enum pmu_wkup_cfg3 { |
| 177 | PMU_GPIO1A_NEGEDGE_WKUP_EN = 0, |
| 178 | PMU_GPIO1B_NEGEDGE_WKUP_EN = 7, |
| 179 | PMU_GPIO1C_NEGEDGE_WKUP_EN = 16, |
| 180 | PMU_GPIO1D_NEGEDGE_WKUP_EN = 24, |
| 181 | }; |
| 182 | |
| 183 | /* pmu_wkup_cfg4 */ |
| 184 | enum pmu_wkup_cfg4 { |
| 185 | PMU_CLUSTER_L_WKUP_EN = 0, |
| 186 | PMU_CLUSTER_B_WKUP_EN, |
| 187 | PMU_GPIO_WKUP_EN, |
| 188 | PMU_SDIO_WKUP_EN, |
| 189 | |
| 190 | PMU_SDMMC_WKUP_EN, |
| 191 | PMU_TIMER_WKUP_EN = 6, |
| 192 | PMU_USBDEV_WKUP_EN, |
| 193 | |
| 194 | PMU_SFT_WKUP_EN, |
| 195 | PMU_M0_WDT_WKUP_EN, |
| 196 | PMU_TIMEOUT_WKUP_EN, |
| 197 | PMU_PWM_WKUP_EN, |
| 198 | |
| 199 | PMU_PCIE_WKUP_EN = 13, |
| 200 | }; |
| 201 | |
| 202 | enum pmu_pwrdn_con { |
| 203 | PMU_A53_L0_PWRDWN_EN = 0, |
| 204 | PMU_A53_L1_PWRDWN_EN, |
| 205 | PMU_A53_L2_PWRDWN_EN, |
| 206 | PMU_A53_L3_PWRDWN_EN, |
| 207 | |
| 208 | PMU_A72_B0_PWRDWN_EN, |
| 209 | PMU_A72_B1_PWRDWN_EN, |
| 210 | PMU_SCU_L_PWRDWN_EN, |
| 211 | PMU_SCU_B_PWRDWN_EN, |
| 212 | |
| 213 | PMU_TCPD0_PWRDWN_EN, |
| 214 | PMU_TCPD1_PWRDWN_EN, |
| 215 | PMU_CCI_PWRDWN_EN, |
| 216 | PMU_PERILP_PWRDWN_EN, |
| 217 | |
| 218 | PMU_PERIHP_PWRDWN_EN, |
| 219 | PMU_CENTER_PWRDWN_EN, |
| 220 | PMU_VIO_PWRDWN_EN, |
| 221 | PMU_GPU_PWRDWN_EN, |
| 222 | |
| 223 | PMU_VCODEC_PWRDWN_EN, |
| 224 | PMU_VDU_PWRDWN_EN, |
| 225 | PMU_RGA_PWRDWN_EN, |
| 226 | PMU_IEP_PWRDWN_EN, |
| 227 | |
| 228 | PMU_VO_PWRDWN_EN, |
| 229 | PMU_ISP0_PWRDWN_EN = 22, |
| 230 | PMU_ISP1_PWRDWN_EN, |
| 231 | |
| 232 | PMU_HDCP_PWRDWN_EN, |
| 233 | PMU_GMAC_PWRDWN_EN, |
| 234 | PMU_EMMC_PWRDWN_EN, |
| 235 | PMU_USB3_PWRDWN_EN, |
| 236 | |
| 237 | PMU_EDP_PWRDWN_EN, |
| 238 | PMU_GIC_PWRDWN_EN, |
| 239 | PMU_SD_PWRDWN_EN, |
| 240 | PMU_SDIOAUDIO_PWRDWN_EN, |
| 241 | }; |
| 242 | |
| 243 | enum pmu_pwrdn_st { |
| 244 | PMU_A53_L0_PWRDWN_ST = 0, |
| 245 | PMU_A53_L1_PWRDWN_ST, |
| 246 | PMU_A53_L2_PWRDWN_ST, |
| 247 | PMU_A53_L3_PWRDWN_ST, |
| 248 | |
| 249 | PMU_A72_B0_PWRDWN_ST, |
| 250 | PMU_A72_B1_PWRDWN_ST, |
| 251 | PMU_SCU_L_PWRDWN_ST, |
| 252 | PMU_SCU_B_PWRDWN_ST, |
| 253 | |
| 254 | PMU_TCPD0_PWRDWN_ST, |
| 255 | PMU_TCPD1_PWRDWN_ST, |
| 256 | PMU_CCI_PWRDWN_ST, |
| 257 | PMU_PERILP_PWRDWN_ST, |
| 258 | |
| 259 | PMU_PERIHP_PWRDWN_ST, |
| 260 | PMU_CENTER_PWRDWN_ST, |
| 261 | PMU_VIO_PWRDWN_ST, |
| 262 | PMU_GPU_PWRDWN_ST, |
| 263 | |
| 264 | PMU_VCODEC_PWRDWN_ST, |
| 265 | PMU_VDU_PWRDWN_ST, |
| 266 | PMU_RGA_PWRDWN_ST, |
| 267 | PMU_IEP_PWRDWN_ST, |
| 268 | |
| 269 | PMU_VO_PWRDWN_ST, |
| 270 | PMU_ISP0_PWRDWN_ST = 22, |
| 271 | PMU_ISP1_PWRDWN_ST, |
| 272 | |
| 273 | PMU_HDCP_PWRDWN_ST, |
| 274 | PMU_GMAC_PWRDWN_ST, |
| 275 | PMU_EMMC_PWRDWN_ST, |
| 276 | PMU_USB3_PWRDWN_ST, |
| 277 | |
| 278 | PMU_EDP_PWRDWN_ST, |
| 279 | PMU_GIC_PWRDWN_ST, |
| 280 | PMU_SD_PWRDWN_ST, |
| 281 | PMU_SDIOAUDIO_PWRDWN_ST, |
| 282 | |
| 283 | }; |
| 284 | |
| 285 | enum pmu_pll_con { |
| 286 | PMU_PLL_PD_CFG = 0, |
| 287 | PMU_SFT_PLL_PD = 8, |
| 288 | }; |
| 289 | |
| 290 | enum pmu_pwermode_con { |
| 291 | PMU_PWR_MODE_EN = 0, |
| 292 | PMU_WKUP_RST_EN, |
| 293 | PMU_INPUT_CLAMP_EN, |
| 294 | PMU_OSC_DIS, |
| 295 | |
| 296 | PMU_ALIVE_USE_LF, |
| 297 | PMU_PMU_USE_LF, |
| 298 | PMU_POWER_OFF_REQ_CFG, |
| 299 | PMU_CHIP_PD_EN, |
| 300 | |
| 301 | PMU_PLL_PD_EN, |
| 302 | PMU_CPU0_PD_EN, |
| 303 | PMU_L2_FLUSH_EN, |
| 304 | PMU_L2_IDLE_EN, |
| 305 | |
| 306 | PMU_SCU_PD_EN, |
| 307 | PMU_CCI_PD_EN, |
| 308 | PMU_PERILP_PD_EN, |
| 309 | PMU_CENTER_PD_EN, |
| 310 | |
| 311 | PMU_SREF0_ENTER_EN, |
| 312 | PMU_DDRC0_GATING_EN, |
| 313 | PMU_DDRIO0_RET_EN, |
| 314 | PMU_DDRIO0_RET_DE_REQ, |
| 315 | |
| 316 | PMU_SREF1_ENTER_EN, |
| 317 | PMU_DDRC1_GATING_EN, |
| 318 | PMU_DDRIO1_RET_EN, |
| 319 | PMU_DDRIO1_RET_DE_REQ, |
| 320 | |
| 321 | PMU_CLK_CENTER_SRC_GATE_EN = 26, |
| 322 | PMU_CLK_PERILP_SRC_GATE_EN, |
| 323 | |
| 324 | PMU_CLK_CORE_SRC_GATE_EN, |
| 325 | PMU_DDRIO_RET_HW_DE_REQ, |
| 326 | PMU_SLP_OUTPUT_CFG, |
| 327 | PMU_MAIN_CLUSTER, |
| 328 | }; |
| 329 | |
| 330 | enum pmu_sft_con { |
| 331 | PMU_WKUP_SFT = 0, |
| 332 | PMU_INPUT_CLAMP_CFG, |
| 333 | PMU_OSC_DIS_CFG, |
| 334 | PMU_PMU_LF_EN_CFG, |
| 335 | |
| 336 | PMU_ALIVE_LF_EN_CFG, |
| 337 | PMU_24M_EN_CFG, |
| 338 | PMU_DBG_PWRUP_L0_CFG, |
| 339 | PMU_WKUP_SFT_M0, |
| 340 | |
| 341 | PMU_DDRCTL0_C_SYSREQ_CFG, |
| 342 | PMU_DDR0_IO_RET_CFG, |
| 343 | |
| 344 | PMU_DDRCTL1_C_SYSREQ_CFG = 12, |
| 345 | PMU_DDR1_IO_RET_CFG, |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 346 | DBG_PWRUP_B0_CFG = 15, |
| 347 | |
| 348 | DBG_NOPWERDWN_L0_EN, |
| 349 | DBG_NOPWERDWN_L1_EN, |
| 350 | DBG_NOPWERDWN_L2_EN, |
| 351 | DBG_NOPWERDWN_L3_EN, |
| 352 | |
| 353 | DBG_PWRUP_REQ_L_EN = 20, |
| 354 | CLUSTER_L_CLK_SRC_GATING_CFG, |
| 355 | L2_FLUSH_REQ_CLUSTER_L, |
| 356 | ACINACTM_CLUSTER_L_CFG, |
| 357 | |
| 358 | DBG_NO_PWERDWN_B0_EN, |
| 359 | DBG_NO_PWERDWN_B1_EN, |
| 360 | |
| 361 | DBG_PWRUP_REQ_B_EN = 28, |
| 362 | CLUSTER_B_CLK_SRC_GATING_CFG, |
| 363 | L2_FLUSH_REQ_CLUSTER_B, |
| 364 | ACINACTM_CLUSTER_B_CFG, |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 365 | }; |
| 366 | |
| 367 | enum pmu_int_con { |
| 368 | PMU_PMU_INT_EN = 0, |
| 369 | PMU_PWRMD_WKUP_INT_EN, |
| 370 | PMU_WKUP_GPIO0_NEG_INT_EN, |
| 371 | PMU_WKUP_GPIO0_POS_INT_EN, |
| 372 | PMU_WKUP_GPIO1_NEG_INT_EN, |
| 373 | PMU_WKUP_GPIO1_POS_INT_EN, |
| 374 | }; |
| 375 | |
| 376 | enum pmu_int_st { |
| 377 | PMU_PWRMD_WKUP_INT_ST = 1, |
| 378 | PMU_WKUP_GPIO0_NEG_INT_ST, |
| 379 | PMU_WKUP_GPIO0_POS_INT_ST, |
| 380 | PMU_WKUP_GPIO1_NEG_INT_ST, |
| 381 | PMU_WKUP_GPIO1_POS_INT_ST, |
| 382 | }; |
| 383 | |
| 384 | enum pmu_gpio0_pos_int_con { |
| 385 | PMU_GPIO0A_POS_INT_EN = 0, |
| 386 | PMU_GPIO0B_POS_INT_EN = 8, |
| 387 | PMU_GPIO0C_POS_INT_EN = 16, |
| 388 | PMU_GPIO0D_POS_INT_EN = 24, |
| 389 | }; |
| 390 | |
| 391 | enum pmu_gpio0_neg_int_con { |
| 392 | PMU_GPIO0A_NEG_INT_EN = 0, |
| 393 | PMU_GPIO0B_NEG_INT_EN = 8, |
| 394 | PMU_GPIO0C_NEG_INT_EN = 16, |
| 395 | PMU_GPIO0D_NEG_INT_EN = 24, |
| 396 | }; |
| 397 | |
| 398 | enum pmu_gpio1_pos_int_con { |
| 399 | PMU_GPIO1A_POS_INT_EN = 0, |
| 400 | PMU_GPIO1B_POS_INT_EN = 8, |
| 401 | PMU_GPIO1C_POS_INT_EN = 16, |
| 402 | PMU_GPIO1D_POS_INT_EN = 24, |
| 403 | }; |
| 404 | |
| 405 | enum pmu_gpio1_neg_int_con { |
| 406 | PMU_GPIO1A_NEG_INT_EN = 0, |
| 407 | PMU_GPIO1B_NEG_INT_EN = 8, |
| 408 | PMU_GPIO1C_NEG_INT_EN = 16, |
| 409 | PMU_GPIO1D_NEG_INT_EN = 24, |
| 410 | }; |
| 411 | |
| 412 | enum pmu_gpio0_pos_int_st { |
| 413 | PMU_GPIO0A_POS_INT_ST = 0, |
| 414 | PMU_GPIO0B_POS_INT_ST = 8, |
| 415 | PMU_GPIO0C_POS_INT_ST = 16, |
| 416 | PMU_GPIO0D_POS_INT_ST = 24, |
| 417 | }; |
| 418 | |
| 419 | enum pmu_gpio0_neg_int_st { |
| 420 | PMU_GPIO0A_NEG_INT_ST = 0, |
| 421 | PMU_GPIO0B_NEG_INT_ST = 8, |
| 422 | PMU_GPIO0C_NEG_INT_ST = 16, |
| 423 | PMU_GPIO0D_NEG_INT_ST = 24, |
| 424 | }; |
| 425 | |
| 426 | enum pmu_gpio1_pos_int_st { |
| 427 | PMU_GPIO1A_POS_INT_ST = 0, |
| 428 | PMU_GPIO1B_POS_INT_ST = 8, |
| 429 | PMU_GPIO1C_POS_INT_ST = 16, |
| 430 | PMU_GPIO1D_POS_INT_ST = 24, |
| 431 | }; |
| 432 | |
| 433 | enum pmu_gpio1_neg_int_st { |
| 434 | PMU_GPIO1A_NEG_INT_ST = 0, |
| 435 | PMU_GPIO1B_NEG_INT_ST = 8, |
| 436 | PMU_GPIO1C_NEG_INT_ST = 16, |
| 437 | PMU_GPIO1D_NEG_INT_ST = 24, |
| 438 | }; |
| 439 | |
| 440 | /* pmu power down configure register 0x0050 */ |
| 441 | enum pmu_pwrdn_inten { |
| 442 | PMU_A53_L0_PWR_SWITCH_INT_EN = 0, |
| 443 | PMU_A53_L1_PWR_SWITCH_INT_EN, |
| 444 | PMU_A53_L2_PWR_SWITCH_INT_EN, |
| 445 | PMU_A53_L3_PWR_SWITCH_INT_EN, |
| 446 | |
| 447 | PMU_A72_B0_PWR_SWITCH_INT_EN, |
| 448 | PMU_A72_B1_PWR_SWITCH_INT_EN, |
| 449 | PMU_SCU_L_PWR_SWITCH_INT_EN, |
| 450 | PMU_SCU_B_PWR_SWITCH_INT_EN, |
| 451 | |
| 452 | PMU_TCPD0_PWR_SWITCH_INT_EN, |
| 453 | PMU_TCPD1_PWR_SWITCH_INT_EN, |
| 454 | PMU_CCI_PWR_SWITCH_INT_EN, |
| 455 | PMU_PERILP_PWR_SWITCH_INT_EN, |
| 456 | |
| 457 | PMU_PERIHP_PWR_SWITCH_INT_EN, |
| 458 | PMU_CENTER_PWR_SWITCH_INT_EN, |
| 459 | PMU_VIO_PWR_SWITCH_INT_EN, |
| 460 | PMU_GPU_PWR_SWITCH_INT_EN, |
| 461 | |
| 462 | PMU_VCODEC_PWR_SWITCH_INT_EN, |
| 463 | PMU_VDU_PWR_SWITCH_INT_EN, |
| 464 | PMU_RGA_PWR_SWITCH_INT_EN, |
| 465 | PMU_IEP_PWR_SWITCH_INT_EN, |
| 466 | |
| 467 | PMU_VO_PWR_SWITCH_INT_EN, |
| 468 | PMU_ISP0_PWR_SWITCH_INT_EN = 22, |
| 469 | PMU_ISP1_PWR_SWITCH_INT_EN, |
| 470 | |
| 471 | PMU_HDCP_PWR_SWITCH_INT_EN, |
| 472 | PMU_GMAC_PWR_SWITCH_INT_EN, |
| 473 | PMU_EMMC_PWR_SWITCH_INT_EN, |
| 474 | PMU_USB3_PWR_SWITCH_INT_EN, |
| 475 | |
| 476 | PMU_EDP_PWR_SWITCH_INT_EN, |
| 477 | PMU_GIC_PWR_SWITCH_INT_EN, |
| 478 | PMU_SD_PWR_SWITCH_INT_EN, |
| 479 | PMU_SDIOAUDIO_PWR_SWITCH_INT_EN, |
| 480 | }; |
| 481 | |
| 482 | enum pmu_wkup_status { |
| 483 | PMU_WKUP_BY_CLSTER_L_INT = 0, |
| 484 | PMU_WKUP_BY_CLSTER_b_INT, |
| 485 | PMU_WKUP_BY_GPIO_INT, |
| 486 | PMU_WKUP_BY_SDIO_DET, |
| 487 | |
| 488 | PMU_WKUP_BY_SDMMC_DET, |
| 489 | PMU_WKUP_BY_TIMER = 6, |
| 490 | PMU_WKUP_BY_USBDEV_DET, |
| 491 | |
| 492 | PMU_WKUP_BY_M0_SFT, |
| 493 | PMU_WKUP_BY_M0_WDT_INT, |
| 494 | PMU_WKUP_BY_TIMEOUT, |
| 495 | PMU_WKUP_BY_PWM, |
| 496 | |
| 497 | PMU_WKUP_BY_PCIE = 13, |
| 498 | }; |
| 499 | |
| 500 | enum pmu_bus_clr { |
| 501 | PMU_CLR_GPU = 0, |
| 502 | PMU_CLR_PERILP, |
| 503 | PMU_CLR_PERIHP, |
| 504 | PMU_CLR_VCODEC, |
| 505 | |
| 506 | PMU_CLR_VDU, |
| 507 | PMU_CLR_RGA, |
| 508 | PMU_CLR_IEP, |
| 509 | PMU_CLR_VOPB, |
| 510 | |
| 511 | PMU_CLR_VOPL, |
| 512 | PMU_CLR_ISP0, |
| 513 | PMU_CLR_ISP1, |
| 514 | PMU_CLR_HDCP, |
| 515 | |
| 516 | PMU_CLR_USB3, |
| 517 | PMU_CLR_PERILPM0, |
| 518 | PMU_CLR_CENTER, |
| 519 | PMU_CLR_CCIM1, |
| 520 | |
| 521 | PMU_CLR_CCIM0, |
| 522 | PMU_CLR_VIO, |
| 523 | PMU_CLR_MSCH0, |
| 524 | PMU_CLR_MSCH1, |
| 525 | |
| 526 | PMU_CLR_ALIVE, |
| 527 | PMU_CLR_PMU, |
| 528 | PMU_CLR_EDP, |
| 529 | PMU_CLR_GMAC, |
| 530 | |
| 531 | PMU_CLR_EMMC, |
| 532 | PMU_CLR_CENTER1, |
| 533 | PMU_CLR_PMUM0, |
| 534 | PMU_CLR_GIC, |
| 535 | |
| 536 | PMU_CLR_SD, |
| 537 | PMU_CLR_SDIOAUDIO, |
| 538 | }; |
| 539 | |
| 540 | /* PMU bus idle request register */ |
| 541 | enum pmu_bus_idle_req { |
| 542 | PMU_IDLE_REQ_GPU = 0, |
| 543 | PMU_IDLE_REQ_PERILP, |
| 544 | PMU_IDLE_REQ_PERIHP, |
| 545 | PMU_IDLE_REQ_VCODEC, |
| 546 | |
| 547 | PMU_IDLE_REQ_VDU, |
| 548 | PMU_IDLE_REQ_RGA, |
| 549 | PMU_IDLE_REQ_IEP, |
| 550 | PMU_IDLE_REQ_VOPB, |
| 551 | |
| 552 | PMU_IDLE_REQ_VOPL, |
| 553 | PMU_IDLE_REQ_ISP0, |
| 554 | PMU_IDLE_REQ_ISP1, |
| 555 | PMU_IDLE_REQ_HDCP, |
| 556 | |
| 557 | PMU_IDLE_REQ_USB3, |
| 558 | PMU_IDLE_REQ_PERILPM0, |
| 559 | PMU_IDLE_REQ_CENTER, |
| 560 | PMU_IDLE_REQ_CCIM0, |
| 561 | |
| 562 | PMU_IDLE_REQ_CCIM1, |
| 563 | PMU_IDLE_REQ_VIO, |
| 564 | PMU_IDLE_REQ_MSCH0, |
| 565 | PMU_IDLE_REQ_MSCH1, |
| 566 | |
| 567 | PMU_IDLE_REQ_ALIVE, |
| 568 | PMU_IDLE_REQ_PMU, |
| 569 | PMU_IDLE_REQ_EDP, |
| 570 | PMU_IDLE_REQ_GMAC, |
| 571 | |
| 572 | PMU_IDLE_REQ_EMMC, |
| 573 | PMU_IDLE_REQ_CENTER1, |
| 574 | PMU_IDLE_REQ_PMUM0, |
| 575 | PMU_IDLE_REQ_GIC, |
| 576 | |
| 577 | PMU_IDLE_REQ_SD, |
| 578 | PMU_IDLE_REQ_SDIOAUDIO, |
| 579 | }; |
| 580 | |
| 581 | /* pmu bus idle status register */ |
| 582 | enum pmu_bus_idle_st { |
| 583 | PMU_IDLE_ST_GPU = 0, |
| 584 | PMU_IDLE_ST_PERILP, |
| 585 | PMU_IDLE_ST_PERIHP, |
| 586 | PMU_IDLE_ST_VCODEC, |
| 587 | |
| 588 | PMU_IDLE_ST_VDU, |
| 589 | PMU_IDLE_ST_RGA, |
| 590 | PMU_IDLE_ST_IEP, |
| 591 | PMU_IDLE_ST_VOPB, |
| 592 | |
| 593 | PMU_IDLE_ST_VOPL, |
| 594 | PMU_IDLE_ST_ISP0, |
| 595 | PMU_IDLE_ST_ISP1, |
| 596 | PMU_IDLE_ST_HDCP, |
| 597 | |
| 598 | PMU_IDLE_ST_USB3, |
| 599 | PMU_IDLE_ST_PERILPM0, |
| 600 | PMU_IDLE_ST_CENTER, |
| 601 | PMU_IDLE_ST_CCIM0, |
| 602 | |
| 603 | PMU_IDLE_ST_CCIM1, |
| 604 | PMU_IDLE_ST_VIO, |
| 605 | PMU_IDLE_ST_MSCH0, |
| 606 | PMU_IDLE_ST_MSCH1, |
| 607 | |
| 608 | PMU_IDLE_ST_ALIVE, |
| 609 | PMU_IDLE_ST_PMU, |
| 610 | PMU_IDLE_ST_EDP, |
| 611 | PMU_IDLE_ST_GMAC, |
| 612 | |
| 613 | PMU_IDLE_ST_EMMC, |
| 614 | PMU_IDLE_ST_CENTER1, |
| 615 | PMU_IDLE_ST_PMUM0, |
| 616 | PMU_IDLE_ST_GIC, |
| 617 | |
| 618 | PMU_IDLE_ST_SD, |
| 619 | PMU_IDLE_ST_SDIOAUDIO, |
| 620 | }; |
| 621 | |
| 622 | enum pmu_bus_idle_ack { |
| 623 | PMU_IDLE_ACK_GPU = 0, |
| 624 | PMU_IDLE_ACK_PERILP, |
| 625 | PMU_IDLE_ACK_PERIHP, |
| 626 | PMU_IDLE_ACK_VCODEC, |
| 627 | |
| 628 | PMU_IDLE_ACK_VDU, |
| 629 | PMU_IDLE_ACK_RGA, |
| 630 | PMU_IDLE_ACK_IEP, |
| 631 | PMU_IDLE_ACK_VOPB, |
| 632 | |
| 633 | PMU_IDLE_ACK_VOPL, |
| 634 | PMU_IDLE_ACK_ISP0, |
| 635 | PMU_IDLE_ACK_ISP1, |
| 636 | PMU_IDLE_ACK_HDCP, |
| 637 | |
| 638 | PMU_IDLE_ACK_USB3, |
| 639 | PMU_IDLE_ACK_PERILPM0, |
| 640 | PMU_IDLE_ACK_CENTER, |
| 641 | PMU_IDLE_ACK_CCIM0, |
| 642 | |
| 643 | PMU_IDLE_ACK_CCIM1, |
| 644 | PMU_IDLE_ACK_VIO, |
| 645 | PMU_IDLE_ACK_MSCH0, |
| 646 | PMU_IDLE_ACK_MSCH1, |
| 647 | |
| 648 | PMU_IDLE_ACK_ALIVE, |
| 649 | PMU_IDLE_ACK_PMU, |
| 650 | PMU_IDLE_ACK_EDP, |
| 651 | PMU_IDLE_ACK_GMAC, |
| 652 | |
| 653 | PMU_IDLE_ACK_EMMC, |
| 654 | PMU_IDLE_ACK_CENTER1, |
| 655 | PMU_IDLE_ACK_PMUM0, |
| 656 | PMU_IDLE_ACK_GIC, |
| 657 | |
| 658 | PMU_IDLE_ACK_SD, |
| 659 | PMU_IDLE_ACK_SDIOAUDIO, |
| 660 | }; |
| 661 | |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 662 | enum pmu_cci500_con { |
| 663 | PMU_PREQ_CCI500_CFG_SW = 0, |
| 664 | PMU_CLR_PREQ_CCI500_HW, |
| 665 | PMU_PSTATE_CCI500_0, |
| 666 | PMU_PSTATE_CCI500_1, |
| 667 | |
| 668 | PMU_PSTATE_CCI500_2, |
| 669 | PMU_QREQ_CCI500_CFG_SW, |
| 670 | PMU_CLR_QREQ_CCI500_HW, |
| 671 | PMU_QGATING_CCI500_CFG, |
| 672 | |
| 673 | PMU_PREQ_CCI500_CFG_SW_WMSK = 16, |
| 674 | PMU_CLR_PREQ_CCI500_HW_WMSK, |
| 675 | PMU_PSTATE_CCI500_0_WMSK, |
| 676 | PMU_PSTATE_CCI500_1_WMSK, |
| 677 | |
| 678 | PMU_PSTATE_CCI500_2_WMSK, |
| 679 | PMU_QREQ_CCI500_CFG_SW_WMSK, |
| 680 | PMU_CLR_QREQ_CCI500_HW_WMSK, |
| 681 | PMU_QGATING_CCI500_CFG_WMSK, |
| 682 | }; |
| 683 | |
| 684 | enum pmu_adb400_con { |
| 685 | PMU_PWRDWN_REQ_CXCS_SW = 0, |
| 686 | PMU_PWRDWN_REQ_CORE_L_SW, |
| 687 | PMU_PWRDWN_REQ_CORE_L_2GIC_SW, |
| 688 | PMU_PWRDWN_REQ_GIC2_CORE_L_SW, |
| 689 | |
| 690 | PMU_PWRDWN_REQ_CORE_B_SW, |
| 691 | PMU_PWRDWN_REQ_CORE_B_2GIC_SW, |
| 692 | PMU_PWRDWN_REQ_GIC2_CORE_B_SW, |
| 693 | |
| 694 | PMU_CLR_CXCS_HW = 8, |
| 695 | PMU_CLR_CORE_L_HW, |
| 696 | PMU_CLR_CORE_L_2GIC_HW, |
| 697 | PMU_CLR_GIC2_CORE_L_HW, |
| 698 | |
| 699 | PMU_CLR_CORE_B_HW, |
| 700 | PMU_CLR_CORE_B_2GIC_HW, |
| 701 | PMU_CLR_GIC2_CORE_B_HW, |
| 702 | |
| 703 | PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16, |
| 704 | PMU_PWRDWN_REQ_CORE_L_SW_WMSK, |
| 705 | PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK, |
| 706 | PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK, |
| 707 | |
| 708 | PMU_PWRDWN_REQ_CORE_B_SW_WMSK, |
| 709 | PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK, |
| 710 | PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK, |
| 711 | |
| 712 | PMU_CLR_CXCS_HW_WMSK = 24, |
| 713 | PMU_CLR_CORE_L_HW_WMSK, |
| 714 | PMU_CLR_CORE_L_2GIC_HW_WMSK, |
| 715 | PMU_CLR_GIC2_CORE_L_HW_WMSK, |
| 716 | |
| 717 | PMU_CLR_CORE_B_HW_WMSK, |
| 718 | PMU_CLR_CORE_B_2GIC_HW_WMSK, |
| 719 | PMU_CLR_GIC2_CORE_B_HW_WMSK, |
| 720 | }; |
| 721 | |
| 722 | enum pmu_adb400_st { |
| 723 | PMU_PWRDWN_REQ_CXCS_SW_ST = 0, |
| 724 | PMU_PWRDWN_REQ_CORE_L_SW_ST, |
| 725 | PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST, |
| 726 | PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST, |
| 727 | |
| 728 | PMU_PWRDWN_REQ_CORE_B_SW_ST, |
| 729 | PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST, |
| 730 | PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST, |
| 731 | |
| 732 | PMU_CLR_CXCS_HW_ST = 8, |
| 733 | PMU_CLR_CORE_L_HW_ST, |
| 734 | PMU_CLR_CORE_L_2GIC_HW_ST, |
| 735 | PMU_CLR_GIC2_CORE_L_HW_ST, |
| 736 | |
| 737 | PMU_CLR_CORE_B_HW_ST, |
| 738 | PMU_CLR_CORE_B_2GIC_HW_ST, |
| 739 | PMU_CLR_GIC2_CORE_B_HW_ST, |
| 740 | }; |
| 741 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 742 | enum pmu_pwrdn_con1 { |
| 743 | PMU_VD_SCU_L_PWRDN_EN = 0, |
| 744 | PMU_VD_SCU_B_PWRDN_EN, |
| 745 | PMU_VD_CENTER_PWRDN_EN, |
| 746 | }; |
| 747 | |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 748 | enum pmu_core_pwr_st { |
| 749 | L2_FLUSHDONE_CLUSTER_L = 0, |
| 750 | STANDBY_BY_WFIL2_CLUSTER_L, |
| 751 | |
| 752 | L2_FLUSHDONE_CLUSTER_B = 10, |
| 753 | STANDBY_BY_WFIL2_CLUSTER_B, |
| 754 | }; |
| 755 | |
Caesar Wang | 0620bb8 | 2016-10-27 01:10:28 +0800 | [diff] [blame] | 756 | /* Specific features required */ |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 757 | #define AP_PWROFF 0x0a |
Caesar Wang | ad39cfe | 2016-07-21 10:36:22 +0800 | [diff] [blame] | 758 | |
Caesar Wang | 3e8548b | 2016-08-25 06:31:32 +0800 | [diff] [blame] | 759 | #define GPIO0A0_SMT_ENABLE BITS_WITH_WMASK(1, 3, 0) |
Caesar Wang | d1b9d2d | 2016-05-25 19:05:19 +0800 | [diff] [blame] | 760 | #define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12) |
Caesar Wang | ad39cfe | 2016-07-21 10:36:22 +0800 | [diff] [blame] | 761 | |
Caesar Wang | d1b9d2d | 2016-05-25 19:05:19 +0800 | [diff] [blame] | 762 | #define TSADC_INT_PIN 38 |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 763 | #define CORES_PM_DISABLE 0x0 |
| 764 | |
| 765 | #define PD_CTR_LOOP 500 |
| 766 | #define CHK_CPU_LOOP 500 |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 767 | #define MAX_WAIT_COUNT 1000 |
| 768 | |
| 769 | #define GRF_SOC_CON4 0x0e210 |
Caesar Wang | 5045a1c | 2016-09-10 02:47:53 +0800 | [diff] [blame] | 770 | |
Caesar Wang | 3e8548b | 2016-08-25 06:31:32 +0800 | [diff] [blame] | 771 | #define PMUGRF_GPIO0A_SMT 0x0120 |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 772 | #define PMUGRF_SOC_CON0 0x0180 |
| 773 | |
| 774 | #define CCI_FORCE_WAKEUP WMSK_BIT(8) |
| 775 | #define EXTERNAL_32K WMSK_BIT(0) |
| 776 | |
| 777 | #define PLL_PD_HW 0xff |
| 778 | #define IOMUX_CLK_32K 0x00030002 |
| 779 | #define NOC_AUTO_ENABLE 0x3fffffff |
| 780 | |
| 781 | #define SAVE_QOS(array, NAME) \ |
| 782 | RK3399_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) |
| 783 | #define RESTORE_QOS(array, NAME) \ |
| 784 | RK3399_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) |
| 785 | |
| 786 | #define RK3399_CPU_AXI_SAVE_QOS(array, base) do { \ |
| 787 | array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \ |
| 788 | array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \ |
| 789 | array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \ |
| 790 | array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \ |
| 791 | array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \ |
| 792 | array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \ |
| 793 | array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \ |
| 794 | } while (0) |
| 795 | |
| 796 | #define RK3399_CPU_AXI_RESTORE_QOS(array, base) do { \ |
| 797 | mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \ |
| 798 | mmio_write_32(base + CPU_AXI_QOS_REVISIONID, array[1]); \ |
| 799 | mmio_write_32(base + CPU_AXI_QOS_PRIORITY, array[2]); \ |
| 800 | mmio_write_32(base + CPU_AXI_QOS_MODE, array[3]); \ |
| 801 | mmio_write_32(base + CPU_AXI_QOS_BANDWIDTH, array[4]); \ |
| 802 | mmio_write_32(base + CPU_AXI_QOS_SATURATION, array[5]); \ |
| 803 | mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \ |
| 804 | } while (0) |
| 805 | |
| 806 | struct pmu_slpdata_s { |
| 807 | uint32_t cci_m0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 808 | uint32_t cci_m1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 809 | uint32_t dmac0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 810 | uint32_t dmac1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 811 | uint32_t dcf_qos[CPU_AXI_QOS_NUM_REGS]; |
| 812 | uint32_t crypto0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 813 | uint32_t crypto1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 814 | uint32_t pmu_cm0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 815 | uint32_t peri_cm1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 816 | uint32_t gic_qos[CPU_AXI_QOS_NUM_REGS]; |
| 817 | uint32_t sdmmc_qos[CPU_AXI_QOS_NUM_REGS]; |
| 818 | uint32_t gmac_qos[CPU_AXI_QOS_NUM_REGS]; |
| 819 | uint32_t emmc_qos[CPU_AXI_QOS_NUM_REGS]; |
| 820 | uint32_t usb_otg0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 821 | uint32_t usb_otg1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 822 | uint32_t usb_host0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 823 | uint32_t usb_host1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 824 | uint32_t gpu_qos[CPU_AXI_QOS_NUM_REGS]; |
| 825 | uint32_t video_m0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 826 | uint32_t video_m1_r_qos[CPU_AXI_QOS_NUM_REGS]; |
| 827 | uint32_t video_m1_w_qos[CPU_AXI_QOS_NUM_REGS]; |
| 828 | uint32_t rga_r_qos[CPU_AXI_QOS_NUM_REGS]; |
| 829 | uint32_t rga_w_qos[CPU_AXI_QOS_NUM_REGS]; |
| 830 | uint32_t vop_big_r[CPU_AXI_QOS_NUM_REGS]; |
| 831 | uint32_t vop_big_w[CPU_AXI_QOS_NUM_REGS]; |
| 832 | uint32_t vop_little[CPU_AXI_QOS_NUM_REGS]; |
| 833 | uint32_t iep_qos[CPU_AXI_QOS_NUM_REGS]; |
| 834 | uint32_t isp1_m0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 835 | uint32_t isp1_m1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 836 | uint32_t isp0_m0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 837 | uint32_t isp0_m1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 838 | uint32_t hdcp_qos[CPU_AXI_QOS_NUM_REGS]; |
| 839 | uint32_t perihp_nsp_qos[CPU_AXI_QOS_NUM_REGS]; |
| 840 | uint32_t perilp_nsp_qos[CPU_AXI_QOS_NUM_REGS]; |
| 841 | uint32_t perilpslv_nsp_qos[CPU_AXI_QOS_NUM_REGS]; |
| 842 | uint32_t sdio_qos[CPU_AXI_QOS_NUM_REGS]; |
| 843 | }; |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 844 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 845 | extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT]; |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 846 | #endif /* __PMU_H__ */ |