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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Soby Mathew52f52b42014-03-12 14:52:51 +000031#include <console.h>
32#include <platform.h>
33#include <pl011.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
Soby Mathew52f52b42014-03-12 14:52:51 +000035static unsigned long uart_base = PL011_BASE;
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
Soby Mathew52f52b42014-03-12 14:52:51 +000037void console_init(unsigned long base_addr)
38{
39 /* Initialise internal base address variable */
40 uart_base = base_addr;
41
42 /* Baud Rate */
43#if defined(PL011_INTEGER) && defined(PL011_FRACTIONAL)
44 pl011_write_ibrd(uart_base, PL011_INTEGER);
45 pl011_write_fbrd(uart_base, PL011_FRACTIONAL);
46#else
47 pl011_setbaudrate(uart_base, PL011_BAUDRATE);
48#endif
49
50 pl011_write_lcr_h(uart_base, PL011_LINE_CONTROL);
51
52 /* Clear any pending errors */
53 pl011_write_ecr(uart_base, 0);
54
55 /* Enable tx, rx, and uart overall */
56 pl011_write_cr(uart_base, PL011_UARTCR_RXE | PL011_UARTCR_TXE |
57 PL011_UARTCR_UARTEN);
58
59}
60
61int console_putc(int c)
62{
63 if (c == '\n')
64 console_putc('\r');
65
66 while ((pl011_read_fr(uart_base) & PL011_UARTFR_TXFF) == 1)
67 ;
68 pl011_write_dr(uart_base, c);
69 return c;
70}
Achin Gupta4f6ad662013-10-25 09:08:21 +010071
Soby Mathew52f52b42014-03-12 14:52:51 +000072int console_getc(void)
73{
74 while ((pl011_read_fr(uart_base) & PL011_UARTFR_RXFE) != 0)
75 ;
76 return pl011_read_dr(uart_base);
77}