blob: ade408d44f5e2b3399c411f3ab61607c8cfd6398 [file] [log] [blame]
Haojian Zhuang3846f142017-05-24 08:49:26 +08001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <debug.h>
8#include <mmio.h>
Isla Mitchelle3631462017-07-14 10:46:32 +01009
10#include <hi6220_regs_acpu.h>
11#include <hi6220_regs_ao.h>
Haojian Zhuang3846f142017-05-24 08:49:26 +080012#include <hisi_ipc.h>
13#include <hisi_pwrc.h>
14#include <hisi_sram_map.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010015
Haojian Zhuang3846f142017-05-24 08:49:26 +080016#include <stdarg.h>
17#include <stdio.h>
18#include <string.h>
19#include <platform_def.h>
20
21#define CLUSTER_CORE_COUNT (4)
22#define CLUSTER_CORE_MASK ((1 << CLUSTER_CORE_COUNT) - 1)
23
24void hisi_pwrc_set_core_bx_addr(unsigned int core, unsigned int cluster,
25 uintptr_t entry_point)
26{
27 uintptr_t *core_entry = (uintptr_t *)PWRCTRL_ACPU_ASM_D_ARM_PARA_AD;
28 unsigned int i;
29
30 if (!core_entry) {
31 INFO("%s: core entry point is null!\n", __func__);
32 return;
33 }
34
35 i = cluster * CLUSTER_CORE_COUNT + core;
36 mmio_write_64((uintptr_t)(core_entry + i), entry_point);
37}
38
39void hisi_pwrc_set_cluster_wfi(unsigned int cluster)
40{
41 unsigned int reg = 0;
42
43 if (cluster == 0) {
44 reg = mmio_read_32(ACPU_SC_SNOOP_PWD);
45 reg |= PD_DETECT_START0;
46 mmio_write_32(ACPU_SC_SNOOP_PWD, reg);
47 } else if (cluster == 1) {
48 reg = mmio_read_32(ACPU_SC_SNOOP_PWD);
49 reg |= PD_DETECT_START1;
50 mmio_write_32(ACPU_SC_SNOOP_PWD, reg);
51 }
52}
53
54int hisi_pwrc_setup(void)
55{
56 unsigned int reg, sec_entrypoint;
57 extern char pm_asm_code[], pm_asm_code_end[];
58 extern char v7_asm[], v7_asm_end[];
59
60 sec_entrypoint = PWRCTRL_ACPU_ASM_CODE_BASE;
61 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(0), sec_entrypoint >> 2);
62 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(1), sec_entrypoint >> 2);
63 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(2), sec_entrypoint >> 2);
64 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(3), sec_entrypoint >> 2);
65 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(4), sec_entrypoint >> 2);
66 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(5), sec_entrypoint >> 2);
67 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(6), sec_entrypoint >> 2);
68 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(7), sec_entrypoint >> 2);
69
70 memset((void *)PWRCTRL_ACPU_ASM_SPACE_ADDR, 0, 0x400);
71 memcpy((void *)PWRCTRL_ACPU_ASM_SPACE_ADDR, (void *)v7_asm,
72 v7_asm_end - v7_asm);
73
74 memcpy((void *)PWRCTRL_ACPU_ASM_CODE_BASE, (void *)pm_asm_code,
75 pm_asm_code_end - pm_asm_code);
76
77 reg = mmio_read_32(AO_SC_SYS_CTRL1);
78 reg |= AO_SC_SYS_CTRL1_REMAP_SRAM_AARM |
79 AO_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK;
80 mmio_write_32(AO_SC_SYS_CTRL1, reg);
81
82 return 0;
83}