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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Vikram Kanigirifbb13012016-02-15 11:54:14 +00002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <arm_def.h>
33#include <bl_common.h>
Dan Handley9df48042015-03-19 18:58:55 +000034#include <console.h>
35#include <platform_def.h>
36#include <plat_arm.h>
Juan Castillob6132f12015-10-06 14:01:35 +010037#include <sp805.h>
Sandrine Bailleux28ee10f2016-06-15 15:44:27 +010038#include <utils.h>
39#include <xlat_tables.h>
Sandrine Bailleuxd7c47502015-10-02 09:32:35 +010040#include "../../../bl1/bl1_private.h"
Dan Handley9df48042015-03-19 18:58:55 +000041
Dan Handley9df48042015-03-19 18:58:55 +000042/* Weak definitions may be overridden in specific ARM standard platform */
43#pragma weak bl1_early_platform_setup
44#pragma weak bl1_plat_arch_setup
45#pragma weak bl1_platform_setup
46#pragma weak bl1_plat_sec_mem_layout
Dan Handley9df48042015-03-19 18:58:55 +000047
48
49/* Data structure which holds the extents of the trusted SRAM for BL1*/
50static meminfo_t bl1_tzram_layout;
51
52meminfo_t *bl1_plat_sec_mem_layout(void)
53{
54 return &bl1_tzram_layout;
55}
56
57/*******************************************************************************
58 * BL1 specific platform actions shared between ARM standard platforms.
59 ******************************************************************************/
60void arm_bl1_early_platform_setup(void)
61{
Dan Handley9df48042015-03-19 18:58:55 +000062
Juan Castillob6132f12015-10-06 14:01:35 +010063#if !ARM_DISABLE_TRUSTED_WDOG
64 /* Enable watchdog */
65 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
66#endif
67
Dan Handley9df48042015-03-19 18:58:55 +000068 /* Initialize the console to provide early debug support */
69 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
70 ARM_CONSOLE_BAUDRATE);
71
72 /* Allow BL1 to see the whole Trusted RAM */
73 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
74 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
75
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010076#if !LOAD_IMAGE_V2
Dan Handley9df48042015-03-19 18:58:55 +000077 /* Calculate how much RAM BL1 is using and how much remains free */
78 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE;
79 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE;
80 reserve_mem(&bl1_tzram_layout.free_base,
81 &bl1_tzram_layout.free_size,
82 BL1_RAM_BASE,
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010083 BL1_RAM_LIMIT - BL1_RAM_BASE);
84#endif /* LOAD_IMAGE_V2 */
Dan Handley9df48042015-03-19 18:58:55 +000085}
86
87void bl1_early_platform_setup(void)
88{
89 arm_bl1_early_platform_setup();
90
91 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000092 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +000093 * No need for locks as no other CPU is active.
94 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000095 plat_arm_interconnect_init();
Dan Handley9df48042015-03-19 18:58:55 +000096 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000097 * Enable Interconnect coherency for the primary CPU's cluster.
Dan Handley9df48042015-03-19 18:58:55 +000098 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000099 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000100}
101
102/******************************************************************************
103 * Perform the very early platform specific architecture setup shared between
104 * ARM standard platforms. This only does basic initialization. Later
105 * architectural setup (bl1_arch_setup()) does not do anything platform
106 * specific.
107 *****************************************************************************/
108void arm_bl1_plat_arch_setup(void)
109{
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100110 arm_setup_page_tables(bl1_tzram_layout.total_base,
Dan Handley9df48042015-03-19 18:58:55 +0000111 bl1_tzram_layout.total_size,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100112 BL_CODE_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900113 BL1_CODE_END,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100114 BL1_RO_DATA_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900115 BL1_RO_DATA_END
Dan Handley9df48042015-03-19 18:58:55 +0000116#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900117 , BL_COHERENT_RAM_BASE,
118 BL_COHERENT_RAM_END
Dan Handley9df48042015-03-19 18:58:55 +0000119#endif
120 );
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100121#ifdef AARCH32
122 enable_mmu_secure(0);
123#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100124 enable_mmu_el3(0);
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100125#endif /* AARCH32 */
Dan Handley9df48042015-03-19 18:58:55 +0000126}
127
128void bl1_plat_arch_setup(void)
129{
130 arm_bl1_plat_arch_setup();
131}
132
133/*
134 * Perform the platform specific architecture setup shared between
135 * ARM standard platforms.
136 */
137void arm_bl1_platform_setup(void)
138{
139 /* Initialise the IO layer and register platform IO devices */
140 plat_arm_io_setup();
141}
142
143void bl1_platform_setup(void)
144{
145 arm_bl1_platform_setup();
146}
147
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000148void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
149{
Juan Castillob6132f12015-10-06 14:01:35 +0100150#if !ARM_DISABLE_TRUSTED_WDOG
151 /* Disable watchdog before leaving BL1 */
152 sp805_stop(ARM_SP805_TWDG_BASE);
153#endif
154
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000155#ifdef EL3_PAYLOAD_BASE
156 /*
157 * Program the EL3 payload's entry point address into the CPUs mailbox
158 * in order to release secondary CPUs from their holding pen and make
159 * them jump there.
160 */
161 arm_program_trusted_mailbox(ep_info->pc);
162 dsbsy();
163 sev();
164#endif
165}