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Nariman Poushin0ece80f2018-02-26 06:52:04 +00001/*
Tamas Ban43e0d922023-05-08 13:41:29 +02002 * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
Nariman Poushin0ece80f2018-02-26 06:52:04 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
9#include <platform_def.h>
10
11#include <common/bl_common.h>
12#include <common/debug.h>
13#include <drivers/arm/ccn.h>
Tamas Ban43e0d922023-05-08 13:41:29 +020014#include <drivers/arm/css/sds.h>
15#include <lib/utils_def.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000016#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <plat/common/platform.h>
Aditya Angadi20b48412019-04-16 11:29:14 +053018#include <drivers/arm/sbsa.h>
19#include <sgi_base_platform_def.h>
Olivier Deprez21cf3602020-07-30 17:18:33 +020020
21#if SPM_MM
Paul Beesley45f40282019-10-15 10:57:42 +000022#include <services/spm_mm_partition.h>
Olivier Deprez21cf3602020-07-30 17:18:33 +020023#endif
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024
Nariman Poushin0ece80f2018-02-26 06:52:04 +000025#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
26 V2M_FLASH0_SIZE, \
27 MT_DEVICE | MT_RO | MT_SECURE)
28/*
29 * Table of regions for different BL stages to map using the MMU.
30 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
31 * arm_configure_mmu_elx() will give the available subset of that.
32 *
33 * Replace or extend the below regions as required
34 */
35#if IMAGE_BL1
36const mmap_region_t plat_arm_mmap[] = {
37 ARM_MAP_SHARED_RAM,
38 SGI_MAP_FLASH0_RO,
39 CSS_SGI_MAP_DEVICE,
40 SOC_CSS_MAP_DEVICE,
41 {0}
42};
43#endif
44#if IMAGE_BL2
45const mmap_region_t plat_arm_mmap[] = {
46 ARM_MAP_SHARED_RAM,
47 SGI_MAP_FLASH0_RO,
Sami Mujawara4f315c2020-04-30 15:50:34 +010048#ifdef PLAT_ARM_MEM_PROT_ADDR
49 ARM_V2M_MAP_MEM_PROTECT,
50#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000051 CSS_SGI_MAP_DEVICE,
52 SOC_CSS_MAP_DEVICE,
53 ARM_MAP_NS_DRAM1,
Aditya Angadica14fb82021-02-17 18:39:32 +053054#if CSS_SGI_CHIP_COUNT > 1
55 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
56#endif
57#if CSS_SGI_CHIP_COUNT > 2
58 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
59#endif
60#if CSS_SGI_CHIP_COUNT > 3
61 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
62#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000063#if ARM_BL31_IN_DRAM
64 ARM_MAP_BL31_SEC_DRAM,
65#endif
Paul Beesleyfe975b42019-09-16 11:29:03 +000066#if SPM_MM
Sughosh Ganue1579e02018-05-16 17:19:56 +053067 ARM_SP_IMAGE_MMAP,
68#endif
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060069#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
John Tsichritzis0c6ee742018-08-22 12:36:37 +010070 ARM_MAP_BL1_RW,
71#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000072 {0}
73};
74#endif
75#if IMAGE_BL31
76const mmap_region_t plat_arm_mmap[] = {
77 ARM_MAP_SHARED_RAM,
78 V2M_MAP_IOFPGA,
79 CSS_SGI_MAP_DEVICE,
Sami Mujawara4f315c2020-04-30 15:50:34 +010080#ifdef PLAT_ARM_MEM_PROT_ADDR
81 ARM_V2M_MAP_MEM_PROTECT,
82#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000083 SOC_CSS_MAP_DEVICE,
Paul Beesleyfe975b42019-09-16 11:29:03 +000084#if SPM_MM
Sughosh Ganue1579e02018-05-16 17:19:56 +053085 ARM_SPM_BUF_EL3_MMAP,
86#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000087 {0}
88};
Sughosh Ganue1579e02018-05-16 17:19:56 +053089
Paul Beesleyfe975b42019-09-16 11:29:03 +000090#if SPM_MM && defined(IMAGE_BL31)
Sughosh Ganue1579e02018-05-16 17:19:56 +053091const mmap_region_t plat_arm_secure_partition_mmap[] = {
Thomas Abrahame4030c02021-02-15 14:14:59 +053092 PLAT_ARM_SECURE_MAP_SYSTEMREG,
93 PLAT_ARM_SECURE_MAP_NOR2,
Rohit Mathew9c07f602021-12-13 15:33:04 +000094 SOC_PLATFORM_SECURE_UART,
Sughosh Ganue1579e02018-05-16 17:19:56 +053095 PLAT_ARM_SECURE_MAP_DEVICE,
96 ARM_SP_IMAGE_MMAP,
97 ARM_SP_IMAGE_NS_BUF_MMAP,
Manish Pandeyf90a73c2023-10-10 15:42:19 +010098#if ENABLE_FEAT_RAS && FFH_SUPPORT
Thomas Abrahama0aea1a2021-02-16 11:36:00 +053099 CSS_SGI_SP_CPER_BUF_MMAP,
100#endif
Sughosh Ganue1579e02018-05-16 17:19:56 +0530101 ARM_SP_IMAGE_RW_MMAP,
102 ARM_SPM_BUF_EL0_MMAP,
103 {0}
104};
Paul Beesleyfe975b42019-09-16 11:29:03 +0000105#endif /* SPM_MM && defined(IMAGE_BL31) */
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000106#endif
107
108ARM_CASSERT_MMAP
Sughosh Ganue1579e02018-05-16 17:19:56 +0530109
Paul Beesleyfe975b42019-09-16 11:29:03 +0000110#if SPM_MM && defined(IMAGE_BL31)
Sughosh Ganue1579e02018-05-16 17:19:56 +0530111/*
112 * Boot information passed to a secure partition during initialisation. Linear
113 * indices in MP information will be filled at runtime.
114 */
Paul Beesley45f40282019-10-15 10:57:42 +0000115static spm_mm_mp_info_t sp_mp_info[] = {
Sughosh Ganue1579e02018-05-16 17:19:56 +0530116 [0] = {0x81000000, 0},
117 [1] = {0x81000100, 0},
118 [2] = {0x81000200, 0},
119 [3] = {0x81000300, 0},
120 [4] = {0x81010000, 0},
121 [5] = {0x81010100, 0},
122 [6] = {0x81010200, 0},
123 [7] = {0x81010300, 0},
124};
125
Paul Beesley45f40282019-10-15 10:57:42 +0000126const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
Sughosh Ganue1579e02018-05-16 17:19:56 +0530127 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
128 .h.version = VERSION_1,
Paul Beesley45f40282019-10-15 10:57:42 +0000129 .h.size = sizeof(spm_mm_boot_info_t),
Sughosh Ganue1579e02018-05-16 17:19:56 +0530130 .h.attr = 0,
131 .sp_mem_base = ARM_SP_IMAGE_BASE,
132 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
133 .sp_image_base = ARM_SP_IMAGE_BASE,
134 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
135 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +0100136 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
Sughosh Ganue1579e02018-05-16 17:19:56 +0530137 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
138 .sp_image_size = ARM_SP_IMAGE_SIZE,
139 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
140 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +0100141 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
Sughosh Ganue1579e02018-05-16 17:19:56 +0530142 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
143 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
144 .num_cpus = PLATFORM_CORE_COUNT,
145 .mp_info = &sp_mp_info[0],
146};
147
148const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
149{
150 return plat_arm_secure_partition_mmap;
151}
152
Paul Beesley45f40282019-10-15 10:57:42 +0000153const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
Sughosh Ganue1579e02018-05-16 17:19:56 +0530154 void *cookie)
155{
156 return &plat_arm_secure_partition_boot_info;
157}
Paul Beesleyfe975b42019-09-16 11:29:03 +0000158#endif /* SPM_MM && defined(IMAGE_BL31) */
John Tsichritzis0c6ee742018-08-22 12:36:37 +0100159
Antonio Nino Diaz9b759862018-09-25 11:38:18 +0100160#if TRUSTED_BOARD_BOOT
John Tsichritzis0c6ee742018-08-22 12:36:37 +0100161int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
162{
163 assert(heap_addr != NULL);
164 assert(heap_size != NULL);
165
166 return arm_get_mbedtls_heap(heap_addr, heap_size);
167}
168#endif
Aditya Angadi20b48412019-04-16 11:29:14 +0530169
170void plat_arm_secure_wdt_start(void)
171{
172 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
173}
174
175void plat_arm_secure_wdt_stop(void)
176{
177 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
178}
Tamas Ban43e0d922023-05-08 13:41:29 +0200179
180static sds_region_desc_t sgi_sds_regions[] = {
181 { .base = PLAT_ARM_SDS_MEM_BASE },
182};
183
184sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)
185{
186 *region_count = ARRAY_SIZE(sgi_sds_regions);
187
188 return sgi_sds_regions;
189}