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Soby Mathewec8ac1c2016-05-05 14:32:05 +01001/*
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
Soby Mathewec8ac1c2016-05-05 14:32:05 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewec8ac1c2016-05-05 14:32:05 +01005 */
6
7#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <lib/xlat_tables/xlat_tables_defs.h>
Soby Mathewec8ac1c2016-05-05 14:32:05 +010010
11OUTPUT_FORMAT(elf32-littlearm)
12OUTPUT_ARCH(arm)
13ENTRY(sp_min_vector_table)
14
15MEMORY {
16 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE
17}
18
19
20SECTIONS
21{
22 . = BL32_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000023 ASSERT(. == ALIGN(PAGE_SIZE),
Soby Mathewec8ac1c2016-05-05 14:32:05 +010024 "BL32_BASE address is not aligned on a page boundary.")
25
26#if SEPARATE_CODE_AND_RODATA
27 .text . : {
28 __TEXT_START__ = .;
29 *entrypoint.o(.text*)
30 *(.text*)
Yatharth Kochar06460cd2016-06-30 15:02:31 +010031 *(.vectors)
Roberto Vargasd93fde32018-04-11 11:53:31 +010032 . = ALIGN(PAGE_SIZE);
Soby Mathewec8ac1c2016-05-05 14:32:05 +010033 __TEXT_END__ = .;
34 } >RAM
35
Roberto Vargas1d04c632018-05-10 11:01:16 +010036 /* .ARM.extab and .ARM.exidx are only added because Clang need them */
37 .ARM.extab . : {
38 *(.ARM.extab* .gnu.linkonce.armextab.*)
39 } >RAM
40
41 .ARM.exidx . : {
42 *(.ARM.exidx* .gnu.linkonce.armexidx.*)
43 } >RAM
44
Soby Mathewec8ac1c2016-05-05 14:32:05 +010045 .rodata . : {
46 __RODATA_START__ = .;
47 *(.rodata*)
48
49 /* Ensure 4-byte alignment for descriptors and ensure inclusion */
50 . = ALIGN(4);
51 __RT_SVC_DESCS_START__ = .;
52 KEEP(*(rt_svc_descs))
53 __RT_SVC_DESCS_END__ = .;
54
55 /*
56 * Ensure 4-byte alignment for cpu_ops so that its fields are also
57 * aligned. Also ensure cpu_ops inclusion.
58 */
59 . = ALIGN(4);
60 __CPU_OPS_START__ = .;
61 KEEP(*(cpu_ops))
62 __CPU_OPS_END__ = .;
63
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010064 /* Place pubsub sections for events */
65 . = ALIGN(8);
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000066#include <lib/el3_runtime/pubsub_events.h>
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010067
Roberto Vargasd93fde32018-04-11 11:53:31 +010068 . = ALIGN(PAGE_SIZE);
Soby Mathewec8ac1c2016-05-05 14:32:05 +010069 __RODATA_END__ = .;
70 } >RAM
71#else
72 ro . : {
73 __RO_START__ = .;
74 *entrypoint.o(.text*)
75 *(.text*)
76 *(.rodata*)
77
78 /* Ensure 4-byte alignment for descriptors and ensure inclusion */
79 . = ALIGN(4);
80 __RT_SVC_DESCS_START__ = .;
81 KEEP(*(rt_svc_descs))
82 __RT_SVC_DESCS_END__ = .;
83
84 /*
85 * Ensure 4-byte alignment for cpu_ops so that its fields are also
86 * aligned. Also ensure cpu_ops inclusion.
87 */
88 . = ALIGN(4);
89 __CPU_OPS_START__ = .;
90 KEEP(*(cpu_ops))
91 __CPU_OPS_END__ = .;
92
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010093 /* Place pubsub sections for events */
94 . = ALIGN(8);
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000095#include <lib/el3_runtime/pubsub_events.h>
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010096
Yatharth Kochar06460cd2016-06-30 15:02:31 +010097 *(.vectors)
Soby Mathewec8ac1c2016-05-05 14:32:05 +010098 __RO_END_UNALIGNED__ = .;
99
100 /*
101 * Memory page(s) mapped to this section will be marked as
102 * read-only, executable. No RW data from the next section must
103 * creep in. Ensure the rest of the current memory block is unused.
104 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100105 . = ALIGN(PAGE_SIZE);
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100106 __RO_END__ = .;
107 } >RAM
108#endif
109
110 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
111 "cpu_ops not defined for this platform.")
112 /*
113 * Define a linker symbol to mark start of the RW memory area for this
114 * image.
115 */
116 __RW_START__ = . ;
117
118 .data . : {
119 __DATA_START__ = .;
120 *(.data*)
121 __DATA_END__ = .;
122 } >RAM
123
Soby Mathewbf169232017-11-14 14:10:10 +0000124#ifdef BL32_PROGBITS_LIMIT
125 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.")
126#endif
127
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100128 stacks (NOLOAD) : {
129 __STACKS_START__ = .;
130 *(tzfw_normal_stacks)
131 __STACKS_END__ = .;
132 } >RAM
133
134 /*
135 * The .bss section gets initialised to 0 at runtime.
Douglas Raillard21362a92016-12-02 13:51:54 +0000136 * Its base address should be 8-byte aligned for better performance of the
137 * zero-initialization code.
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100138 */
Douglas Raillard21362a92016-12-02 13:51:54 +0000139 .bss (NOLOAD) : ALIGN(8) {
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100140 __BSS_START__ = .;
141 *(.bss*)
142 *(COMMON)
143#if !USE_COHERENT_MEM
144 /*
145 * Bakery locks are stored in normal .bss memory
146 *
147 * Each lock's data is spread across multiple cache lines, one per CPU,
148 * but multiple locks can share the same cache line.
149 * The compiler will allocate enough memory for one CPU's bakery locks,
150 * the remaining cache lines are allocated by the linker script
151 */
152 . = ALIGN(CACHE_WRITEBACK_GRANULE);
153 __BAKERY_LOCK_START__ = .;
154 *(bakery_lock)
155 . = ALIGN(CACHE_WRITEBACK_GRANULE);
156 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
157 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
158 __BAKERY_LOCK_END__ = .;
159#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
160 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE,
161 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
162#endif
163#endif
164
165#if ENABLE_PMF
166 /*
167 * Time-stamps are stored in normal .bss memory
168 *
169 * The compiler will allocate enough memory for one CPU's time-stamps,
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000170 * the remaining memory for other CPUs is allocated by the
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100171 * linker script
172 */
173 . = ALIGN(CACHE_WRITEBACK_GRANULE);
174 __PMF_TIMESTAMP_START__ = .;
175 KEEP(*(pmf_timestamp_array))
176 . = ALIGN(CACHE_WRITEBACK_GRANULE);
177 __PMF_PERCPU_TIMESTAMP_END__ = .;
178 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__);
179 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1));
180 __PMF_TIMESTAMP_END__ = .;
181#endif /* ENABLE_PMF */
182
183 __BSS_END__ = .;
184 } >RAM
185
186 /*
187 * The xlat_table section is for full, aligned page tables (4K).
188 * Removing them from .bss avoids forcing 4K alignment on
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +0000189 * the .bss section. The tables are initialized to zero by the translation
190 * tables library.
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100191 */
192 xlat_table (NOLOAD) : {
193 *(xlat_table)
194 } >RAM
195
196 __BSS_SIZE__ = SIZEOF(.bss);
197
198#if USE_COHERENT_MEM
199 /*
200 * The base address of the coherent memory section must be page-aligned (4K)
201 * to guarantee that the coherent data are stored on their own pages and
202 * are not mixed with normal data. This is required to set up the correct
203 * memory attributes for the coherent data page tables.
204 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000205 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100206 __COHERENT_RAM_START__ = .;
207 /*
208 * Bakery locks are stored in coherent memory
209 *
210 * Each lock's data is contiguous and fully allocated by the compiler
211 */
212 *(bakery_lock)
213 *(tzfw_coherent_mem)
214 __COHERENT_RAM_END_UNALIGNED__ = .;
215 /*
216 * Memory page(s) mapped to this section will be marked
217 * as device memory. No other unexpected data must creep in.
218 * Ensure the rest of the current memory page is unused.
219 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100220 . = ALIGN(PAGE_SIZE);
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100221 __COHERENT_RAM_END__ = .;
222 } >RAM
223
224 __COHERENT_RAM_UNALIGNED_SIZE__ =
225 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
226#endif
227
228 /*
229 * Define a linker symbol to mark end of the RW memory area for this
230 * image.
231 */
232 __RW_END__ = .;
233
234 __BL32_END__ = .;
235}