Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 5a70094 | 2019-01-23 16:54:12 -0800 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 6 | */ |
| 7 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <assert.h> |
| 9 | #include <errno.h> |
Scott Branden | e5dcf98 | 2020-08-25 13:49:32 -0700 | [diff] [blame] | 10 | #include <inttypes.h> |
| 11 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | #include <string.h> |
| 13 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 14 | #include <arch.h> |
| 15 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | #include <common/bl_common.h> |
| 17 | #include <common/debug.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 18 | #include <context.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 19 | #include <denver.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 20 | #include <lib/el3_runtime/context_mgmt.h> |
| 21 | #include <lib/mmio.h> |
| 22 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 23 | #include <mce.h> |
Varun Wadekar | b556828 | 2016-12-13 18:04:35 -0800 | [diff] [blame] | 24 | #include <mce_private.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 25 | #include <t18x_ari.h> |
| 26 | #include <tegra_def.h> |
Varun Wadekar | efa66d4 | 2016-07-18 17:42:02 -0700 | [diff] [blame] | 27 | #include <tegra_platform.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 28 | |
| 29 | /* NVG functions handlers */ |
| 30 | static arch_mce_ops_t nvg_mce_ops = { |
| 31 | .enter_cstate = nvg_enter_cstate, |
| 32 | .update_cstate_info = nvg_update_cstate_info, |
| 33 | .update_crossover_time = nvg_update_crossover_time, |
| 34 | .read_cstate_stats = nvg_read_cstate_stats, |
| 35 | .write_cstate_stats = nvg_write_cstate_stats, |
| 36 | .call_enum_misc = ari_enumeration_misc, |
| 37 | .is_ccx_allowed = nvg_is_ccx_allowed, |
| 38 | .is_sc7_allowed = nvg_is_sc7_allowed, |
| 39 | .online_core = nvg_online_core, |
| 40 | .cc3_ctrl = nvg_cc3_ctrl, |
| 41 | .update_reset_vector = ari_reset_vector_update, |
| 42 | .roc_flush_cache = ari_roc_flush_cache, |
| 43 | .roc_flush_cache_trbits = ari_roc_flush_cache_trbits, |
| 44 | .roc_clean_cache = ari_roc_clean_cache, |
| 45 | .read_write_mca = ari_read_write_mca, |
| 46 | .update_ccplex_gsc = ari_update_ccplex_gsc, |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 47 | .enter_ccplex_state = ari_enter_ccplex_state, |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 48 | .read_write_uncore_perfmon = ari_read_write_uncore_perfmon, |
| 49 | .misc_ccplex = ari_misc_ccplex |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | /* ARI functions handlers */ |
| 53 | static arch_mce_ops_t ari_mce_ops = { |
| 54 | .enter_cstate = ari_enter_cstate, |
| 55 | .update_cstate_info = ari_update_cstate_info, |
| 56 | .update_crossover_time = ari_update_crossover_time, |
| 57 | .read_cstate_stats = ari_read_cstate_stats, |
| 58 | .write_cstate_stats = ari_write_cstate_stats, |
| 59 | .call_enum_misc = ari_enumeration_misc, |
| 60 | .is_ccx_allowed = ari_is_ccx_allowed, |
| 61 | .is_sc7_allowed = ari_is_sc7_allowed, |
| 62 | .online_core = ari_online_core, |
| 63 | .cc3_ctrl = ari_cc3_ctrl, |
| 64 | .update_reset_vector = ari_reset_vector_update, |
| 65 | .roc_flush_cache = ari_roc_flush_cache, |
| 66 | .roc_flush_cache_trbits = ari_roc_flush_cache_trbits, |
| 67 | .roc_clean_cache = ari_roc_clean_cache, |
| 68 | .read_write_mca = ari_read_write_mca, |
| 69 | .update_ccplex_gsc = ari_update_ccplex_gsc, |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 70 | .enter_ccplex_state = ari_enter_ccplex_state, |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 71 | .read_write_uncore_perfmon = ari_read_write_uncore_perfmon, |
| 72 | .misc_ccplex = ari_misc_ccplex |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 73 | }; |
| 74 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 75 | typedef struct { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 76 | uint32_t ari_base; |
| 77 | arch_mce_ops_t *ops; |
| 78 | } mce_config_t; |
| 79 | |
| 80 | /* Table to hold the per-CPU ARI base address and function handlers */ |
| 81 | static mce_config_t mce_cfg_table[MCE_ARI_APERTURES_MAX] = { |
| 82 | { |
| 83 | /* A57 Core 0 */ |
| 84 | .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_0_OFFSET, |
| 85 | .ops = &ari_mce_ops, |
| 86 | }, |
| 87 | { |
| 88 | /* A57 Core 1 */ |
| 89 | .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_1_OFFSET, |
| 90 | .ops = &ari_mce_ops, |
| 91 | }, |
| 92 | { |
| 93 | /* A57 Core 2 */ |
| 94 | .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_2_OFFSET, |
| 95 | .ops = &ari_mce_ops, |
| 96 | }, |
| 97 | { |
| 98 | /* A57 Core 3 */ |
| 99 | .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_3_OFFSET, |
| 100 | .ops = &ari_mce_ops, |
| 101 | }, |
| 102 | { |
| 103 | /* D15 Core 0 */ |
| 104 | .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_4_OFFSET, |
| 105 | .ops = &nvg_mce_ops, |
| 106 | }, |
| 107 | { |
| 108 | /* D15 Core 1 */ |
| 109 | .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_5_OFFSET, |
| 110 | .ops = &nvg_mce_ops, |
| 111 | } |
| 112 | }; |
| 113 | |
| 114 | static uint32_t mce_get_curr_cpu_ari_base(void) |
| 115 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 116 | uint64_t mpidr = read_mpidr(); |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 117 | uint64_t cpuid = mpidr & MPIDR_CPU_MASK; |
| 118 | uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 119 | |
| 120 | /* |
| 121 | * T186 has 2 CPU clusters, one with Denver CPUs and the other with |
| 122 | * ARM CortexA-57 CPUs. Each cluster consists of 4 CPUs and the CPU |
| 123 | * numbers start from 0. In order to get the proper arch_mce_ops_t |
| 124 | * struct, we have to convert the Denver CPU ids to the corresponding |
| 125 | * indices in the mce_ops_table array. |
| 126 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 127 | if (impl == DENVER_IMPL) { |
| 128 | cpuid |= 0x4U; |
| 129 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 130 | |
| 131 | return mce_cfg_table[cpuid].ari_base; |
| 132 | } |
| 133 | |
| 134 | static arch_mce_ops_t *mce_get_curr_cpu_ops(void) |
| 135 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 136 | uint64_t mpidr = read_mpidr(); |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 137 | uint64_t cpuid = mpidr & MPIDR_CPU_MASK; |
| 138 | uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & |
| 139 | MIDR_IMPL_MASK; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 140 | |
| 141 | /* |
| 142 | * T186 has 2 CPU clusters, one with Denver CPUs and the other with |
| 143 | * ARM CortexA-57 CPUs. Each cluster consists of 4 CPUs and the CPU |
| 144 | * numbers start from 0. In order to get the proper arch_mce_ops_t |
| 145 | * struct, we have to convert the Denver CPU ids to the corresponding |
| 146 | * indices in the mce_ops_table array. |
| 147 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 148 | if (impl == DENVER_IMPL) { |
| 149 | cpuid |= 0x4U; |
| 150 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 151 | |
| 152 | return mce_cfg_table[cpuid].ops; |
| 153 | } |
| 154 | |
| 155 | /******************************************************************************* |
| 156 | * Common handler for all MCE commands |
| 157 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 158 | int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 159 | uint64_t arg2) |
| 160 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 161 | const arch_mce_ops_t *ops; |
| 162 | gp_regs_t *gp_regs = get_gpregs_ctx(cm_get_context(NON_SECURE)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 163 | uint32_t cpu_ari_base; |
| 164 | uint64_t ret64 = 0, arg3, arg4, arg5; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 165 | int32_t ret = 0; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 166 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 167 | assert(gp_regs != NULL); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 168 | |
| 169 | /* get a pointer to the CPU's arch_mce_ops_t struct */ |
| 170 | ops = mce_get_curr_cpu_ops(); |
| 171 | |
| 172 | /* get the CPU's ARI base address */ |
| 173 | cpu_ari_base = mce_get_curr_cpu_ari_base(); |
| 174 | |
| 175 | switch (cmd) { |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 176 | case (uint64_t)MCE_CMD_ENTER_CSTATE: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 177 | ret = ops->enter_cstate(cpu_ari_base, arg0, arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 178 | |
| 179 | break; |
| 180 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 181 | case (uint64_t)MCE_CMD_UPDATE_CSTATE_INFO: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 182 | /* |
| 183 | * get the parameters required for the update cstate info |
| 184 | * command |
| 185 | */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 186 | arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4); |
| 187 | arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5); |
| 188 | arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 189 | |
| 190 | ret = ops->update_cstate_info(cpu_ari_base, (uint32_t)arg0, |
| 191 | (uint32_t)arg1, (uint32_t)arg2, (uint8_t)arg3, |
| 192 | (uint32_t)arg4, (uint8_t)arg5); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 193 | |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 194 | write_ctx_reg(gp_regs, CTX_GPREG_X4, (0ULL)); |
| 195 | write_ctx_reg(gp_regs, CTX_GPREG_X5, (0ULL)); |
| 196 | write_ctx_reg(gp_regs, CTX_GPREG_X6, (0ULL)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 197 | |
| 198 | break; |
| 199 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 200 | case (uint64_t)MCE_CMD_UPDATE_CROSSOVER_TIME: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 201 | ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 202 | |
| 203 | break; |
| 204 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 205 | case (uint64_t)MCE_CMD_READ_CSTATE_STATS: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 206 | ret64 = ops->read_cstate_stats(cpu_ari_base, arg0); |
| 207 | |
| 208 | /* update context to return cstate stats value */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 209 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); |
| 210 | write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 211 | |
| 212 | break; |
| 213 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 214 | case (uint64_t)MCE_CMD_WRITE_CSTATE_STATS: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 215 | ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 216 | |
| 217 | break; |
| 218 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 219 | case (uint64_t)MCE_CMD_IS_CCX_ALLOWED: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 220 | ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 221 | |
| 222 | /* update context to return CCx status value */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 223 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)(ret)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 224 | |
| 225 | break; |
| 226 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 227 | case (uint64_t)MCE_CMD_IS_SC7_ALLOWED: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 228 | ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 229 | |
| 230 | /* update context to return SC7 status value */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 231 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)(ret)); |
| 232 | write_ctx_reg(gp_regs, CTX_GPREG_X3, (uint64_t)(ret)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 233 | |
| 234 | break; |
| 235 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 236 | case (uint64_t)MCE_CMD_ONLINE_CORE: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 237 | ret = ops->online_core(cpu_ari_base, arg0); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 238 | |
| 239 | break; |
| 240 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 241 | case (uint64_t)MCE_CMD_CC3_CTRL: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 242 | ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 243 | |
| 244 | break; |
| 245 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 246 | case (uint64_t)MCE_CMD_ECHO_DATA: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 247 | ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_ECHO, |
| 248 | arg0); |
| 249 | |
| 250 | /* update context to return if echo'd data matched source */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 251 | write_ctx_reg(gp_regs, CTX_GPREG_X1, ((ret64 == arg0) ? |
| 252 | 1ULL : 0ULL)); |
| 253 | write_ctx_reg(gp_regs, CTX_GPREG_X2, ((ret64 == arg0) ? |
| 254 | 1ULL : 0ULL)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 255 | |
| 256 | break; |
| 257 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 258 | case (uint64_t)MCE_CMD_READ_VERSIONS: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 259 | ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION, |
| 260 | arg0); |
| 261 | |
| 262 | /* |
| 263 | * version = minor(63:32) | major(31:0). Update context |
| 264 | * to return major and minor version number. |
| 265 | */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 266 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); |
| 267 | write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64 >> 32ULL)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 268 | |
| 269 | break; |
| 270 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 271 | case (uint64_t)MCE_CMD_ENUM_FEATURES: |
Krishna Sitaraman | fc2ec16 | 2016-07-27 16:26:45 -0700 | [diff] [blame] | 272 | ret64 = ops->call_enum_misc(cpu_ari_base, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 273 | TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0); |
| 274 | |
| 275 | /* update context to return features value */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 276 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 277 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 278 | break; |
| 279 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 280 | case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE_TRBITS: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 281 | ret = ops->roc_flush_cache_trbits(cpu_ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 282 | |
| 283 | break; |
| 284 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 285 | case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 286 | ret = ops->roc_flush_cache(cpu_ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 287 | |
| 288 | break; |
| 289 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 290 | case (uint64_t)MCE_CMD_ROC_CLEAN_CACHE: |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 291 | ret = ops->roc_clean_cache(cpu_ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 292 | |
| 293 | break; |
| 294 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 295 | case (uint64_t)MCE_CMD_ENUM_READ_MCA: |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 296 | ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 297 | |
| 298 | /* update context to return MCA data/error */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 299 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); |
| 300 | write_ctx_reg(gp_regs, CTX_GPREG_X2, (arg1)); |
| 301 | write_ctx_reg(gp_regs, CTX_GPREG_X3, (ret64)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 302 | |
| 303 | break; |
| 304 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 305 | case (uint64_t)MCE_CMD_ENUM_WRITE_MCA: |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 306 | ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 307 | |
| 308 | /* update context to return MCA error */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 309 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); |
| 310 | write_ctx_reg(gp_regs, CTX_GPREG_X3, (ret64)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 311 | |
| 312 | break; |
| 313 | |
Varun Wadekar | ad2824f | 2016-03-28 13:44:35 -0700 | [diff] [blame] | 314 | #if ENABLE_CHIP_VERIFICATION_HARNESS |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 315 | case (uint64_t)MCE_CMD_ENABLE_LATIC: |
Varun Wadekar | ad2824f | 2016-03-28 13:44:35 -0700 | [diff] [blame] | 316 | /* |
| 317 | * This call is not for production use. The constant value, |
| 318 | * 0xFFFF0000, is specific to allowing for enabling LATIC on |
| 319 | * pre-production parts for the chip verification harness. |
| 320 | * |
| 321 | * Enabling LATIC allows S/W to read the MINI ISPs in the |
| 322 | * CCPLEX. The ISMs are used for various measurements relevant |
| 323 | * to particular locations in the Silicon. They are small |
| 324 | * counters which can be polled to determine how fast a |
| 325 | * particular location in the Silicon is. |
| 326 | */ |
| 327 | ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(), |
| 328 | 0xFFFF0000); |
| 329 | |
| 330 | break; |
| 331 | #endif |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 332 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 333 | case (uint64_t)MCE_CMD_UNCORE_PERFMON_REQ: |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 334 | ret = ops->read_write_uncore_perfmon(cpu_ari_base, arg0, &arg1); |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 335 | |
| 336 | /* update context to return data */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 337 | write_ctx_reg(gp_regs, CTX_GPREG_X1, (arg1)); |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 338 | break; |
| 339 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 340 | case (uint64_t)MCE_CMD_MISC_CCPLEX: |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 341 | ops->misc_ccplex(cpu_ari_base, arg0, arg1); |
| 342 | |
| 343 | break; |
| 344 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 345 | default: |
Scott Branden | e5dcf98 | 2020-08-25 13:49:32 -0700 | [diff] [blame] | 346 | ERROR("unknown MCE command (%" PRIu64 ")\n", cmd); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 347 | ret = EINVAL; |
| 348 | break; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 349 | } |
| 350 | |
| 351 | return ret; |
| 352 | } |
| 353 | |
| 354 | /******************************************************************************* |
| 355 | * Handler to update the reset vector for CPUs |
| 356 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 357 | int32_t mce_update_reset_vector(void) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 358 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 359 | const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 360 | |
Krishna Sitaraman | d007f76 | 2016-09-02 16:53:04 -0700 | [diff] [blame] | 361 | ops->update_reset_vector(mce_get_curr_cpu_ari_base()); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 362 | |
| 363 | return 0; |
| 364 | } |
| 365 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 366 | static int32_t mce_update_ccplex_gsc(tegra_ari_gsc_index_t gsc_idx) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 367 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 368 | const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 369 | |
| 370 | ops->update_ccplex_gsc(mce_get_curr_cpu_ari_base(), gsc_idx); |
| 371 | |
| 372 | return 0; |
| 373 | } |
| 374 | |
| 375 | /******************************************************************************* |
| 376 | * Handler to update carveout values for Video Memory Carveout region |
| 377 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 378 | int32_t mce_update_gsc_videomem(void) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 379 | { |
| 380 | return mce_update_ccplex_gsc(TEGRA_ARI_GSC_VPR_IDX); |
| 381 | } |
| 382 | |
| 383 | /******************************************************************************* |
| 384 | * Handler to update carveout values for TZDRAM aperture |
| 385 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 386 | int32_t mce_update_gsc_tzdram(void) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 387 | { |
| 388 | return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZ_DRAM_IDX); |
| 389 | } |
| 390 | |
| 391 | /******************************************************************************* |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 392 | * Handler to shutdown/reset the entire system |
| 393 | ******************************************************************************/ |
| 394 | __dead2 void mce_enter_ccplex_state(uint32_t state_idx) |
| 395 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 396 | const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 397 | |
| 398 | /* sanity check state value */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 399 | if ((state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) && |
| 400 | (state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT)) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 401 | panic(); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 402 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 403 | |
| 404 | ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(), state_idx); |
| 405 | |
| 406 | /* wait till the CCPLEX powers down */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 407 | for (;;) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 408 | ; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 409 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 410 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 411 | } |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 412 | |
| 413 | /******************************************************************************* |
Varun Wadekar | c47504f | 2017-03-23 17:32:20 -0700 | [diff] [blame] | 414 | * Handler to issue the UPDATE_CSTATE_INFO request |
| 415 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 416 | void mce_update_cstate_info(const mce_cstate_info_t *cstate) |
Varun Wadekar | c47504f | 2017-03-23 17:32:20 -0700 | [diff] [blame] | 417 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 418 | const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); |
Varun Wadekar | c47504f | 2017-03-23 17:32:20 -0700 | [diff] [blame] | 419 | |
| 420 | /* issue the UPDATE_CSTATE_INFO request */ |
| 421 | ops->update_cstate_info(mce_get_curr_cpu_ari_base(), cstate->cluster, |
| 422 | cstate->ccplex, cstate->system, cstate->system_state_force, |
| 423 | cstate->wake_mask, cstate->update_wake_mask); |
| 424 | } |
| 425 | |
| 426 | /******************************************************************************* |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 427 | * Handler to read the MCE firmware version and check if it is compatible |
| 428 | * with interface header the BL3-1 was compiled against |
| 429 | ******************************************************************************/ |
| 430 | void mce_verify_firmware_version(void) |
| 431 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 432 | const arch_mce_ops_t *ops; |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 433 | uint32_t cpu_ari_base; |
| 434 | uint64_t version; |
Varun Wadekar | efa66d4 | 2016-07-18 17:42:02 -0700 | [diff] [blame] | 435 | uint32_t major, minor; |
| 436 | |
| 437 | /* |
Varun Wadekar | b556828 | 2016-12-13 18:04:35 -0800 | [diff] [blame] | 438 | * MCE firmware is not supported on simulation platforms. |
Varun Wadekar | efa66d4 | 2016-07-18 17:42:02 -0700 | [diff] [blame] | 439 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 440 | if (tegra_platform_is_emulation()) { |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 441 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 442 | INFO("MCE firmware is not supported\n"); |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 443 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 444 | } else { |
| 445 | /* get a pointer to the CPU's arch_mce_ops_t struct */ |
| 446 | ops = mce_get_curr_cpu_ops(); |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 447 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 448 | /* get the CPU's ARI base address */ |
| 449 | cpu_ari_base = mce_get_curr_cpu_ari_base(); |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 450 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 451 | /* |
| 452 | * Read the MCE firmware version and extract the major and minor |
| 453 | * version fields |
| 454 | */ |
| 455 | version = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION, 0); |
| 456 | major = (uint32_t)version; |
| 457 | minor = (uint32_t)(version >> 32); |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 458 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 459 | INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor, |
| 460 | TEGRA_ARI_VERSION_MAJOR, TEGRA_ARI_VERSION_MINOR); |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 461 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 462 | /* |
| 463 | * Verify that the MCE firmware version and the interface header |
| 464 | * match |
| 465 | */ |
| 466 | if (major != TEGRA_ARI_VERSION_MAJOR) { |
| 467 | ERROR("ARI major version mismatch\n"); |
| 468 | panic(); |
| 469 | } |
| 470 | |
| 471 | if (minor < TEGRA_ARI_VERSION_MINOR) { |
| 472 | ERROR("ARI minor version mismatch\n"); |
| 473 | panic(); |
| 474 | } |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 475 | } |
| 476 | } |