Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 1 | /* |
Vishnu Banavath | 2b651ea | 2022-01-19 18:43:12 +0000 | [diff] [blame] | 2 | * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <common/tbbr/tbbr_img_def.h> |
| 11 | #include <lib/utils_def.h> |
| 12 | #include <lib/xlat_tables/xlat_tables_defs.h> |
| 13 | #include <plat/arm/board/common/v2m_def.h> |
| 14 | #include <plat/arm/common/arm_spm_def.h> |
| 15 | #include <plat/arm/common/smccc_def.h> |
| 16 | #include <plat/common/common_def.h> |
| 17 | #include <plat/arm/soc/common/soc_css_def.h> |
| 18 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 19 | #define ARM_ROTPK_HEADER_LEN 19 |
| 20 | #define ARM_ROTPK_HASH_LEN 32 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 21 | |
| 22 | /* Special value used to verify platform parameters from BL2 to BL31 */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 23 | #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 24 | |
| 25 | /* PL011 UART related constants */ |
| 26 | #ifdef V2M_IOFPGA_UART0_CLK_IN_HZ |
| 27 | #undef V2M_IOFPGA_UART0_CLK_IN_HZ |
| 28 | #endif |
| 29 | |
| 30 | #ifdef V2M_IOFPGA_UART1_CLK_IN_HZ |
| 31 | #undef V2M_IOFPGA_UART1_CLK_IN_HZ |
| 32 | #endif |
| 33 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 34 | #define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000 |
| 35 | #define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 36 | |
Vishnu Banavath | 2b651ea | 2022-01-19 18:43:12 +0000 | [diff] [blame] | 37 | /* Core/Cluster/Thread counts for corstone1000 */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 38 | #define CORSTONE1000_CLUSTER_COUNT U(1) |
| 39 | #define CORSTONE1000_MAX_CPUS_PER_CLUSTER U(4) |
| 40 | #define CORSTONE1000_MAX_PE_PER_CPU U(1) |
| 41 | #define CORSTONE1000_PRIMARY_CPU U(0) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 42 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 43 | #define PLAT_ARM_CLUSTER_COUNT CORSTONE1000_CLUSTER_COUNT |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 44 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 45 | #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ |
| 46 | CORSTONE1000_MAX_CPUS_PER_CLUSTER * \ |
| 47 | CORSTONE1000_MAX_PE_PER_CPU) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 48 | |
| 49 | /* UART related constants */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 50 | #define PLAT_ARM_BOOT_UART_BASE 0x1a510000 |
| 51 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ |
| 52 | #define PLAT_ARM_RUN_UART_BASE 0x1a520000 |
| 53 | #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ |
| 54 | #define ARM_CONSOLE_BAUDRATE 115200 |
| 55 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE |
| 56 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 57 | |
| 58 | /* Memory related constants */ |
| 59 | |
| 60 | /* SRAM (CVM) memory layout |
| 61 | * |
| 62 | * <ARM_TRUSTED_SRAM_BASE> |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 63 | * partition size: sizeof(meminfo_t) = 16 bytes |
| 64 | * content: memory info area used by the next BL |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 65 | * |
| 66 | * <ARM_FW_CONFIG_BASE> |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 67 | * partition size: 4080 bytes |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 68 | * |
| 69 | * <ARM_BL2_MEM_DESC_BASE> |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 70 | * partition size: 4 KB |
| 71 | * content: Area where BL2 copies the images descriptors |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 72 | * |
| 73 | * <ARM_BL_RAM_BASE> = <BL32_BASE> |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 74 | * partition size: 688 KB |
| 75 | * content: BL32 (optee-os) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 76 | * |
Vishnu Banavath | 2b651ea | 2022-01-19 18:43:12 +0000 | [diff] [blame] | 77 | * <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x20ae000 |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 78 | * partition size: 8 KB |
| 79 | * content: BL32 config (TOS_FW_CONFIG) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 80 | * |
| 81 | * <BL31_BASE> |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 82 | * partition size: 140 KB |
| 83 | * content: BL31 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 84 | * |
| 85 | * <BL2_SIGNATURE_BASE> |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 86 | * partition size: 4 KB |
| 87 | * content: MCUBOOT data needed to verify TF-A BL2 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 88 | * |
| 89 | * <BL2_BASE> |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 90 | * partition size: 176 KB |
| 91 | * content: BL2 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 92 | * |
| 93 | * <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 94 | * partition size: 512 KB |
| 95 | * content: BL33 (u-boot) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 96 | */ |
| 97 | |
| 98 | /* DDR memory */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 99 | #define ARM_DRAM1_BASE UL(0x80000000) |
| 100 | #define ARM_DRAM1_SIZE (SZ_2G) /* 2GB*/ |
| 101 | #define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 102 | |
Vishnu Banavath | 2b651ea | 2022-01-19 18:43:12 +0000 | [diff] [blame] | 103 | /* DRAM1 and DRAM2 are the same for corstone1000 */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 104 | #define ARM_DRAM2_BASE ARM_DRAM1_BASE |
| 105 | #define ARM_DRAM2_SIZE ARM_DRAM1_SIZE |
| 106 | #define ARM_DRAM2_END ARM_DRAM1_END |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 107 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 108 | #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE |
| 109 | #define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE |
| 110 | #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE - 1) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 111 | |
| 112 | /* The first 8 KB of Trusted SRAM are used as shared memory */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 113 | #define ARM_TRUSTED_SRAM_BASE UL(0x02000000) |
| 114 | #define ARM_SHARED_RAM_SIZE (SZ_8K) /* 8 KB */ |
| 115 | #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 116 | |
| 117 | /* The remaining Trusted SRAM is used to load the BL images */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 118 | #define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */ |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 119 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 120 | /* Last 512KB of CVM is allocated for shared RAM as an example openAMP */ |
| 121 | #define ARM_NS_SHARED_RAM_SIZE (512 * SZ_1K) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 122 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 123 | #define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \ |
| 124 | ARM_NS_SHARED_RAM_SIZE - \ |
| 125 | ARM_SHARED_RAM_SIZE) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 126 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 127 | #define PLAT_ARM_MAX_BL2_SIZE (180 * SZ_1K) /* 180 KB */ |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 128 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 129 | #define PLAT_ARM_MAX_BL31_SIZE (140 * SZ_1K) /* 140 KB */ |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 130 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 131 | #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE) |
| 132 | #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ |
| 133 | ARM_SHARED_RAM_SIZE) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 134 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 135 | #define BL2_SIGNATURE_SIZE (SZ_4K) /* 4 KB */ |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 136 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 137 | #define BL2_SIGNATURE_BASE (BL2_LIMIT - PLAT_ARM_MAX_BL2_SIZE) |
| 138 | #define BL2_BASE (BL2_LIMIT - \ |
| 139 | PLAT_ARM_MAX_BL2_SIZE + \ |
| 140 | BL2_SIGNATURE_SIZE) |
| 141 | #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 142 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 143 | #define BL31_BASE (BL2_SIGNATURE_BASE - PLAT_ARM_MAX_BL31_SIZE) |
| 144 | #define BL31_LIMIT BL2_SIGNATURE_BASE |
Arpita S.K | 639f7b7 | 2021-10-13 14:49:26 +0530 | [diff] [blame] | 145 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 146 | #define CORSTONE1000_TOS_FW_CONFIG_BASE (BL31_BASE - \ |
| 147 | CORSTONE1000_TOS_FW_CONFIG_SIZE) |
| 148 | #define CORSTONE1000_TOS_FW_CONFIG_SIZE (SZ_8K) /* 8 KB */ |
| 149 | #define CORSTONE1000_TOS_FW_CONFIG_LIMIT BL31_BASE |
Arpita S.K | 639f7b7 | 2021-10-13 14:49:26 +0530 | [diff] [blame] | 150 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 151 | #define BL32_BASE ARM_BL_RAM_BASE |
| 152 | #define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - BL32_BASE) |
Arpita S.K | 639f7b7 | 2021-10-13 14:49:26 +0530 | [diff] [blame] | 153 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 154 | #define BL32_LIMIT (BL32_BASE + PLAT_ARM_MAX_BL32_SIZE) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 155 | |
| 156 | /* SPD_spmd settings */ |
| 157 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 158 | #define PLAT_ARM_SPMC_BASE BL32_BASE |
| 159 | #define PLAT_ARM_SPMC_SIZE PLAT_ARM_MAX_BL32_SIZE |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 160 | |
| 161 | /* NS memory */ |
| 162 | |
Arpita S.K | 639f7b7 | 2021-10-13 14:49:26 +0530 | [diff] [blame] | 163 | /* The last 512KB of the SRAM is allocated as shared memory */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 164 | #define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \ |
| 165 | (PLAT_ARM_MAX_BL31_SIZE + \ |
| 166 | PLAT_ARM_MAX_BL32_SIZE)) |
Arpita S.K | 639f7b7 | 2021-10-13 14:49:26 +0530 | [diff] [blame] | 167 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 168 | #define BL33_BASE ARM_DRAM1_BASE |
| 169 | #define PLAT_ARM_MAX_BL33_SIZE (12 * SZ_1M) /* 12 MB*/ |
| 170 | #define BL33_LIMIT (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 171 | |
| 172 | /* end of the definition of SRAM memory layout */ |
| 173 | |
| 174 | /* NOR Flash */ |
| 175 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 176 | #define PLAT_ARM_BOOT_BANK_FLAG UL(0x08002000) |
| 177 | #define PLAT_ARM_FIP_BASE_BANK0 UL(0x081EF000) |
| 178 | #define PLAT_ARM_FIP_BASE_BANK1 UL(0x0916F000) |
| 179 | #define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 180 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 181 | #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE |
| 182 | #define PLAT_ARM_NVM_SIZE (SZ_32M) /* 32 MB */ |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 183 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 184 | #define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE_BANK0 |
| 185 | #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 186 | |
| 187 | /* |
| 188 | * Some data must be aligned on the biggest cache line size in the platform. |
| 189 | * This is known only to the platform as it might have a combination of |
| 190 | * integrated and external caches. |
| 191 | */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 192 | #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) |
| 193 | #define ARM_CACHE_WRITEBACK_SHIFT 6 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 194 | |
| 195 | /* |
| 196 | * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo. |
| 197 | * FW_CONFIG is intended to host the device tree. Currently, This area is not |
Vishnu Banavath | 2b651ea | 2022-01-19 18:43:12 +0000 | [diff] [blame] | 198 | * used because corstone1000 platform doesn't use a device tree at TF-A level. |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 199 | */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 200 | #define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE + sizeof(meminfo_t)) |
| 201 | #define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE + \ |
| 202 | (ARM_SHARED_RAM_SIZE >> 1)) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 203 | |
| 204 | /* |
| 205 | * Boot parameters passed from BL2 to BL31/BL32 are stored here |
| 206 | */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 207 | #define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT |
| 208 | #define ARM_BL2_MEM_DESC_LIMIT ARM_BL_RAM_BASE |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 209 | |
| 210 | /* |
| 211 | * The max number of regions like RO(code), coherent and data required by |
| 212 | * different BL stages which need to be mapped in the MMU. |
| 213 | */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 214 | #define ARM_BL_REGIONS 3 |
| 215 | #define PLAT_ARM_MMAP_ENTRIES 8 |
| 216 | #define MAX_XLAT_TABLES 5 |
| 217 | #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) |
| 218 | #define MAX_IO_DEVICES 2 |
| 219 | #define MAX_IO_HANDLES 3 |
| 220 | #define MAX_IO_BLOCK_DEVICES 1 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 221 | |
| 222 | /* GIC related constants */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 223 | #define PLAT_ARM_GICD_BASE 0x1C010000 |
| 224 | #define PLAT_ARM_GICC_BASE 0x1C02F000 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 225 | |
| 226 | /* MHUv2 Secure Channel receiver and sender */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 227 | #define PLAT_SDK700_MHU0_SEND 0x1B800000 |
| 228 | #define PLAT_SDK700_MHU0_RECV 0x1B810000 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 229 | |
| 230 | /* Timer/watchdog related constants */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 231 | #define ARM_SYS_CNTCTL_BASE UL(0x1a200000) |
| 232 | #define ARM_SYS_CNTREAD_BASE UL(0x1a210000) |
| 233 | #define ARM_SYS_TIMCTL_BASE UL(0x1a220000) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 234 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 235 | #define SECURE_WATCHDOG_ADDR_CTRL_REG 0x1A320000 |
| 236 | #define SECURE_WATCHDOG_ADDR_VAL_REG 0x1A320008 |
| 237 | #define SECURE_WATCHDOG_MASK_ENABLE 0x01 |
| 238 | #define SECURE_WATCHDOG_COUNTDOWN_VAL 0x1000 |
Emekcan Aras | 53e91a3 | 2021-11-17 18:45:32 +0000 | [diff] [blame] | 239 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 240 | #define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 241 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 242 | #define CORSTONE1000_IRQ_TZ_WDOG 32 |
| 243 | #define CORSTONE1000_IRQ_SEC_SYS_TIMER 34 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 244 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 245 | #define PLAT_MAX_PWR_LVL 2 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 246 | /* |
| 247 | * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The |
| 248 | * power levels have a 1:1 mapping with the MPIDR affinity levels. |
| 249 | */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 250 | #define ARM_PWR_LVL0 MPIDR_AFFLVL0 |
| 251 | #define ARM_PWR_LVL1 MPIDR_AFFLVL1 |
| 252 | #define ARM_PWR_LVL2 MPIDR_AFFLVL2 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 253 | |
| 254 | /* |
| 255 | * Macros for local power states in ARM platforms encoded by State-ID field |
| 256 | * within the power-state parameter. |
| 257 | */ |
| 258 | /* Local power state for power domains in Run state. */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 259 | #define ARM_LOCAL_STATE_RUN U(0) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 260 | /* Local power state for retention. Valid only for CPU power domains */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 261 | #define ARM_LOCAL_STATE_RET U(1) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 262 | /* Local power state for OFF/power-down. Valid for CPU and cluster |
| 263 | * power domains |
| 264 | */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 265 | #define ARM_LOCAL_STATE_OFF U(2) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 266 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 267 | #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE |
| 268 | #define PLAT_ARM_NSTIMER_FRAME_ID U(1) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 269 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 270 | #define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 271 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 272 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 273 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 274 | |
| 275 | /* |
| 276 | * This macro defines the deepest retention state possible. A higher state |
| 277 | * ID will represent an invalid or a power down state. |
| 278 | */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 279 | #define PLAT_MAX_RET_STATE 1 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 280 | |
| 281 | /* |
| 282 | * This macro defines the deepest power down states possible. Any state ID |
| 283 | * higher than this is invalid. |
| 284 | */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 285 | #define PLAT_MAX_OFF_STATE 2 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 286 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 287 | #define PLATFORM_STACK_SIZE UL(0x440) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 288 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 289 | #define CORSTONE1000_EXTERNAL_FLASH MAP_REGION_FLAT( \ |
| 290 | PLAT_ARM_NVM_BASE, \ |
| 291 | PLAT_ARM_NVM_SIZE, \ |
| 292 | MT_DEVICE | MT_RO | MT_SECURE) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 293 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 294 | #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ |
| 295 | ARM_SHARED_RAM_BASE, \ |
| 296 | ARM_SHARED_RAM_SIZE, \ |
| 297 | MT_MEMORY | MT_RW | MT_SECURE) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 298 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 299 | #define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \ |
| 300 | ARM_NS_SHARED_RAM_BASE, \ |
| 301 | ARM_NS_SHARED_RAM_SIZE, \ |
| 302 | MT_MEMORY | MT_RW | MT_NS) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 303 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 304 | #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ |
| 305 | ARM_NS_DRAM1_BASE, \ |
| 306 | ARM_NS_DRAM1_SIZE, \ |
| 307 | MT_MEMORY | MT_RW | MT_NS) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 308 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 309 | #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ |
| 310 | BL_CODE_BASE, \ |
| 311 | (BL_CODE_END - BL_CODE_BASE), \ |
| 312 | MT_CODE | MT_SECURE), \ |
| 313 | MAP_REGION_FLAT( \ |
| 314 | BL_RO_DATA_BASE, \ |
| 315 | (BL_RO_DATA_END - BL_RO_DATA_BASE), \ |
| 316 | MT_RO_DATA | MT_SECURE) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 317 | #if USE_COHERENT_MEM |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 318 | #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ |
| 319 | BL_COHERENT_RAM_BASE, \ |
| 320 | (BL_COHERENT_RAM_END \ |
| 321 | - BL_COHERENT_RAM_BASE), \ |
| 322 | MT_DEVICE | MT_RW | MT_SECURE) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 323 | #endif |
| 324 | |
| 325 | /* |
| 326 | * Map the region for the optional device tree configuration with read and |
| 327 | * write permissions |
| 328 | */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 329 | #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ |
| 330 | ARM_FW_CONFIG_BASE, \ |
| 331 | (ARM_FW_CONFIG_LIMIT \ |
| 332 | - ARM_FW_CONFIG_BASE), \ |
| 333 | MT_MEMORY | MT_RW | MT_SECURE) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 334 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 335 | #define CORSTONE1000_DEVICE_BASE (0x1A000000) |
| 336 | #define CORSTONE1000_DEVICE_SIZE (0x26000000) |
| 337 | #define CORSTONE1000_MAP_DEVICE MAP_REGION_FLAT( \ |
| 338 | CORSTONE1000_DEVICE_BASE, \ |
| 339 | CORSTONE1000_DEVICE_SIZE, \ |
| 340 | MT_DEVICE | MT_RW | MT_SECURE) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 341 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 342 | #define ARM_IRQ_SEC_PHY_TIMER 29 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 343 | |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 344 | #define ARM_IRQ_SEC_SGI_0 8 |
| 345 | #define ARM_IRQ_SEC_SGI_1 9 |
| 346 | #define ARM_IRQ_SEC_SGI_2 10 |
| 347 | #define ARM_IRQ_SEC_SGI_3 11 |
| 348 | #define ARM_IRQ_SEC_SGI_4 12 |
| 349 | #define ARM_IRQ_SEC_SGI_5 13 |
| 350 | #define ARM_IRQ_SEC_SGI_6 14 |
| 351 | #define ARM_IRQ_SEC_SGI_7 15 |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 352 | |
| 353 | /* |
| 354 | * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 |
| 355 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 356 | * as Group 0 interrupts. |
| 357 | */ |
| 358 | #define ARM_G1S_IRQ_PROPS(grp) \ |
| 359 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ |
| 360 | (grp), GIC_INTR_CFG_LEVEL), \ |
| 361 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ |
| 362 | (grp), GIC_INTR_CFG_EDGE), \ |
| 363 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ |
| 364 | (grp), GIC_INTR_CFG_EDGE), \ |
| 365 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ |
| 366 | (grp), GIC_INTR_CFG_EDGE), \ |
| 367 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ |
| 368 | (grp), GIC_INTR_CFG_EDGE), \ |
| 369 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ |
| 370 | (grp), GIC_INTR_CFG_EDGE), \ |
| 371 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ |
| 372 | (grp), GIC_INTR_CFG_EDGE) |
| 373 | |
| 374 | #define ARM_G0_IRQ_PROPS(grp) \ |
| 375 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 376 | GIC_INTR_CFG_EDGE) |
| 377 | |
| 378 | /* |
| 379 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 380 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 381 | * as Group 0 interrupts. |
| 382 | */ |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 383 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 384 | ARM_G1S_IRQ_PROPS(grp), \ |
| 385 | INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, \ |
| 386 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 387 | (grp), GIC_INTR_CFG_LEVEL), \ |
| 388 | INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \ |
| 389 | GIC_HIGHEST_SEC_PRIORITY, \ |
| 390 | (grp), GIC_INTR_CFG_LEVEL) |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 391 | |
| 392 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 393 | |
| 394 | #endif /* PLATFORM_DEF_H */ |