Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 2 | * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 9 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | |
| 11 | #include <bl32/sp_min/platform_sp_min.h> |
| 12 | #include <common/bl_common.h> |
| 13 | #include <common/debug.h> |
| 14 | #include <drivers/arm/pl011.h> |
| 15 | #include <drivers/console.h> |
| 16 | #include <lib/mmio.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 17 | #include <plat/arm/common/plat_arm.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 18 | #include <plat/common/platform.h> |
| 19 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 20 | static entry_point_info_t bl33_image_ep_info; |
| 21 | |
| 22 | /* Weak definitions may be overridden in specific ARM standard platform */ |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 23 | #pragma weak sp_min_platform_setup |
| 24 | #pragma weak sp_min_plat_arch_setup |
Soby Mathew | 6d07e67 | 2018-03-01 10:53:33 +0000 | [diff] [blame] | 25 | #pragma weak plat_arm_sp_min_early_platform_setup |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 26 | |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 27 | #define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \ |
| 28 | BL32_BASE, \ |
| 29 | BL32_END - BL32_BASE, \ |
| 30 | MT_MEMORY | MT_RW | MT_SECURE) |
| 31 | |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 32 | /* |
| 33 | * Check that BL32_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page |
| 34 | * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. |
| 35 | */ |
| 36 | CASSERT(BL32_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl32_base_overflows); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 37 | |
| 38 | /******************************************************************************* |
| 39 | * Return a pointer to the 'entry_point_info' structure of the next image for the |
| 40 | * security state specified. BL33 corresponds to the non-secure image type |
| 41 | * while BL32 corresponds to the secure image type. A NULL pointer is returned |
| 42 | * if the image does not exist. |
| 43 | ******************************************************************************/ |
| 44 | entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) |
| 45 | { |
| 46 | entry_point_info_t *next_image_info; |
| 47 | |
| 48 | next_image_info = &bl33_image_ep_info; |
| 49 | |
| 50 | /* |
| 51 | * None of the images on the ARM development platforms can have 0x0 |
| 52 | * as the entrypoint |
| 53 | */ |
| 54 | if (next_image_info->pc) |
| 55 | return next_image_info; |
| 56 | else |
| 57 | return NULL; |
| 58 | } |
| 59 | |
| 60 | /******************************************************************************* |
Soby Mathew | 6d07e67 | 2018-03-01 10:53:33 +0000 | [diff] [blame] | 61 | * Utility function to perform early platform setup. |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 62 | ******************************************************************************/ |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 63 | void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, |
| 64 | uintptr_t hw_config, void *plat_params_from_bl2) |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 65 | { |
| 66 | /* Initialize the console to provide early debug support */ |
Daniel Boulby | 05e7f56 | 2018-09-19 13:58:20 +0100 | [diff] [blame] | 67 | arm_console_boot_init(); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 68 | |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 69 | #if RESET_TO_SP_MIN |
| 70 | /* There are no parameters from BL2 if SP_MIN is a reset vector */ |
| 71 | assert(from_bl2 == NULL); |
| 72 | assert(plat_params_from_bl2 == NULL); |
| 73 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 74 | /* Populate entry point information for BL33 */ |
| 75 | SET_PARAM_HEAD(&bl33_image_ep_info, |
| 76 | PARAM_EP, |
| 77 | VERSION_1, |
| 78 | 0); |
| 79 | /* |
| 80 | * Tell SP_MIN where the non-trusted software image |
| 81 | * is located and the entry state information |
| 82 | */ |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 83 | bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 84 | bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); |
| 85 | SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 86 | |
Manish Pandey | 37c4ec2 | 2018-11-02 13:28:25 +0000 | [diff] [blame] | 87 | # if ARM_LINUX_KERNEL_AS_BL33 |
| 88 | /* |
| 89 | * According to the file ``Documentation/arm/Booting`` of the Linux |
| 90 | * kernel tree, Linux expects: |
| 91 | * r0 = 0 |
| 92 | * r1 = machine type number, optional in DT-only platforms (~0 if so) |
| 93 | * r2 = Physical address of the device tree blob |
| 94 | */ |
| 95 | bl33_image_ep_info.args.arg0 = 0U; |
| 96 | bl33_image_ep_info.args.arg1 = ~0U; |
| 97 | bl33_image_ep_info.args.arg2 = (u_register_t)ARM_PRELOADED_DTB_BASE; |
| 98 | # endif |
| 99 | |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 100 | #else /* RESET_TO_SP_MIN */ |
| 101 | |
| 102 | /* |
| 103 | * Check params passed from BL2 should not be NULL, |
| 104 | */ |
| 105 | bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; |
| 106 | assert(params_from_bl2 != NULL); |
| 107 | assert(params_from_bl2->h.type == PARAM_BL_PARAMS); |
| 108 | assert(params_from_bl2->h.version >= VERSION_2); |
| 109 | |
| 110 | bl_params_node_t *bl_params = params_from_bl2->head; |
| 111 | |
| 112 | /* |
| 113 | * Copy BL33 entry point information. |
| 114 | * They are stored in Secure RAM, in BL2's address space. |
| 115 | */ |
| 116 | while (bl_params) { |
| 117 | if (bl_params->image_id == BL33_IMAGE_ID) { |
| 118 | bl33_image_ep_info = *bl_params->ep_info; |
| 119 | break; |
| 120 | } |
| 121 | |
| 122 | bl_params = bl_params->next_params_info; |
| 123 | } |
| 124 | |
| 125 | if (bl33_image_ep_info.pc == 0) |
| 126 | panic(); |
| 127 | |
| 128 | #endif /* RESET_TO_SP_MIN */ |
| 129 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 130 | } |
| 131 | |
Soby Mathew | 6d07e67 | 2018-03-01 10:53:33 +0000 | [diff] [blame] | 132 | /******************************************************************************* |
| 133 | * Default implementation for sp_min_platform_setup2() for ARM platforms |
| 134 | ******************************************************************************/ |
| 135 | void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 136 | u_register_t arg2, u_register_t arg3) |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 137 | { |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 138 | arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 139 | |
| 140 | /* |
| 141 | * Initialize Interconnect for this cluster during cold boot. |
| 142 | * No need for locks as no other CPU is active. |
| 143 | */ |
| 144 | plat_arm_interconnect_init(); |
| 145 | |
| 146 | /* |
| 147 | * Enable Interconnect coherency for the primary CPU's cluster. |
| 148 | * Earlier bootloader stages might already do this (e.g. Trusted |
| 149 | * Firmware's BL1 does it) but we can't assume so. There is no harm in |
| 150 | * executing this code twice anyway. |
| 151 | * Platform specific PSCI code will enable coherency for other |
| 152 | * clusters. |
| 153 | */ |
| 154 | plat_arm_interconnect_enter_coherency(); |
| 155 | } |
| 156 | |
Soby Mathew | 6d07e67 | 2018-03-01 10:53:33 +0000 | [diff] [blame] | 157 | void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, |
| 158 | u_register_t arg2, u_register_t arg3) |
| 159 | { |
| 160 | plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); |
| 161 | } |
| 162 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 163 | /******************************************************************************* |
Dimitris Papastamos | 52323b0 | 2017-06-07 13:45:41 +0100 | [diff] [blame] | 164 | * Perform any SP_MIN platform runtime setup prior to SP_MIN exit. |
| 165 | * Common to ARM standard platforms. |
| 166 | ******************************************************************************/ |
| 167 | void arm_sp_min_plat_runtime_setup(void) |
| 168 | { |
| 169 | /* Initialize the runtime console */ |
Daniel Boulby | 05e7f56 | 2018-09-19 13:58:20 +0100 | [diff] [blame] | 170 | arm_console_runtime_init(); |
Dimitris Papastamos | 52323b0 | 2017-06-07 13:45:41 +0100 | [diff] [blame] | 171 | } |
| 172 | |
| 173 | /******************************************************************************* |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 174 | * Perform platform specific setup for SP_MIN |
| 175 | ******************************************************************************/ |
| 176 | void sp_min_platform_setup(void) |
| 177 | { |
| 178 | /* Initialize the GIC driver, cpu and distributor interfaces */ |
| 179 | plat_arm_gic_driver_init(); |
| 180 | plat_arm_gic_init(); |
| 181 | |
| 182 | /* |
| 183 | * Do initial security configuration to allow DRAM/device access |
| 184 | * (if earlier BL has not already done so). |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 185 | */ |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 186 | #if RESET_TO_SP_MIN |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 187 | plat_arm_security_setup(); |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 188 | |
| 189 | #if defined(PLAT_ARM_MEM_PROT_ADDR) |
| 190 | arm_nor_psci_do_dyn_mem_protect(); |
| 191 | #endif /* PLAT_ARM_MEM_PROT_ADDR */ |
| 192 | |
Yatharth Kochar | 1c16a4c | 2016-06-30 14:50:58 +0100 | [diff] [blame] | 193 | #endif |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 194 | |
| 195 | /* Enable and initialize the System level generic timer */ |
| 196 | mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, |
Antonio Nino Diaz | e0b757d | 2018-08-24 16:30:29 +0100 | [diff] [blame] | 197 | CNTCR_FCREQ(0U) | CNTCR_EN); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 198 | |
| 199 | /* Allow access to the System counter timer module */ |
| 200 | arm_configure_sys_timer(); |
| 201 | |
| 202 | /* Initialize power controller before setting up topology */ |
| 203 | plat_arm_pwrc_setup(); |
| 204 | } |
| 205 | |
Dimitris Papastamos | 52323b0 | 2017-06-07 13:45:41 +0100 | [diff] [blame] | 206 | void sp_min_plat_runtime_setup(void) |
| 207 | { |
| 208 | arm_sp_min_plat_runtime_setup(); |
| 209 | } |
| 210 | |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 211 | /******************************************************************************* |
| 212 | * Perform the very early platform specific architectural setup here. At the |
| 213 | * moment this only initializes the MMU |
| 214 | ******************************************************************************/ |
| 215 | void sp_min_plat_arch_setup(void) |
| 216 | { |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 217 | const mmap_region_t bl_regions[] = { |
| 218 | MAP_BL_SP_MIN_TOTAL, |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 219 | ARM_MAP_BL_RO, |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 220 | #if USE_COHERENT_MEM |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 221 | ARM_MAP_BL_COHERENT_RAM, |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 222 | #endif |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 223 | {0} |
| 224 | }; |
| 225 | |
Roberto Vargas | 344ff02 | 2018-10-19 16:44:18 +0100 | [diff] [blame] | 226 | setup_page_tables(bl_regions, plat_arm_get_mmap()); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 227 | |
Antonio Nino Diaz | 533d3a8 | 2018-08-07 16:35:19 +0100 | [diff] [blame] | 228 | enable_mmu_svc_mon(0); |
Soby Mathew | 7b75418 | 2016-07-11 14:15:27 +0100 | [diff] [blame] | 229 | } |