blob: c65e29e977013a7223fc4a50e9a768cb5d186626 [file] [log] [blame]
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <bl_common.h>
10#include <console.h>
11#include <debug.h>
12#include <errno.h>
13#include <generic_delay_timer.h>
14#include <mmio.h>
15#include <pl061_gpio.h>
16#include <platform.h>
17#include <platform_def.h>
18#include <string.h>
19#include <tbbr_img_def.h>
20#include "../../bl1/bl1_private.h"
21#include "hi3798cv200.h"
22#include "plat_private.h"
23
24/* Symbols from link script for conherent section */
25extern unsigned long __COHERENT_RAM_START__;
26extern unsigned long __COHERENT_RAM_END__;
27
28#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
29#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
30
31/* Data structure which holds the extents of the trusted RAM for BL1 */
32static meminfo_t bl1_tzram_layout;
33
34meminfo_t *bl1_plat_sec_mem_layout(void)
35{
36 return &bl1_tzram_layout;
37}
38
39void bl1_early_platform_setup(void)
40{
41 /* Initialize the console to provide early debug support */
42 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
43
44 /* Allow BL1 to see the whole Trusted RAM */
45 bl1_tzram_layout.total_base = BL_MEM_BASE;
46 bl1_tzram_layout.total_size = BL_MEM_SIZE;
47
48 /* Calculate how much RAM BL1 is using and how much remains free */
49 bl1_tzram_layout.free_base = BL_MEM_BASE;
50 bl1_tzram_layout.free_size = BL_MEM_SIZE;
51
52 reserve_mem(&bl1_tzram_layout.free_base,
53 &bl1_tzram_layout.free_size,
54 BL1_RAM_BASE,
55 BL1_RAM_LIMIT - BL1_RAM_BASE);
56
57 INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
58 BL1_RAM_LIMIT - BL1_RAM_BASE);
59}
60
61void bl1_plat_arch_setup(void)
62{
63 plat_configure_mmu_el3(bl1_tzram_layout.total_base,
64 bl1_tzram_layout.total_size,
65 BL_MEM_BASE, /* l-loader and BL1 ROM */
66 BL1_RO_LIMIT,
67 BL1_COHERENT_RAM_BASE,
68 BL1_COHERENT_RAM_LIMIT);
69}
70
71void bl1_platform_setup(void)
72{
73 int i;
74
75 generic_delay_timer_init();
76
77 pl061_gpio_init();
78 for (i = 0; i < GPIO_MAX; i++)
79 pl061_gpio_register(GPIO_BASE(i), i);
80
81 plat_io_setup();
82}
83
84unsigned int bl1_plat_get_next_image_id(void)
85{
86 return BL2_IMAGE_ID;
87}