blob: dcb4edd482daaab1d2a32dd2317ba3d8ae73cf9c [file] [log] [blame]
Yatharth Kocharf528faf2016-06-28 16:58:26 +01001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __EL3_COMMON_MACROS_S__
32#define __EL3_COMMON_MACROS_S__
33
34#include <arch.h>
35#include <asm_macros.S>
36#include <assert_macros.S>
37
38 /*
39 * Helper macro to initialise EL3 registers we care about.
40 */
41 .macro el3_arch_init_common _exception_vectors
42 /* ---------------------------------------------------------------------
43 * Enable the instruction cache and alignment checks
44 * ---------------------------------------------------------------------
45 */
46 ldr r1, =(SCTLR_RES1 | SCTLR_I_BIT | SCTLR_A_BIT)
47 ldcopr r0, SCTLR
48 orr r0, r0, r1
49 stcopr r0, SCTLR
50 isb
51
52 /* ---------------------------------------------------------------------
53 * Set the exception vectors (VBAR/MVBAR).
54 * ---------------------------------------------------------------------
55 */
56 ldr r0, =\_exception_vectors
57 stcopr r0, VBAR
58 stcopr r0, MVBAR
59 isb
60
61 /* -----------------------------------------------------
62 * Enable the SIF bit to disable instruction fetches
63 * from Non-secure memory.
64 * -----------------------------------------------------
65 */
66 ldcopr r0, SCR
67 orr r0, r0, #SCR_SIF_BIT
68 stcopr r0, SCR
69
70 /* -----------------------------------------------------
71 * Enable the Asynchronous data abort now that the
72 * exception vectors have been setup.
73 * -----------------------------------------------------
74 */
75 cpsie a
76 isb
77
78 /* Enable access to Advanced SIMD registers */
79 ldcopr r0, NSACR
80 bic r0, r0, #NSASEDIS_BIT
81 bic r0, r0, #NSTRCDIS_BIT
82 orr r0, r0, #(NASCR_CP10_BIT | NASCR_CP11_BIT)
83 stcopr r0, NSACR
84 isb
85
86 /*
87 * Enable access to Advanced SIMD, Floating point and to the Trace
88 * functionality as well.
89 */
90 ldcopr r0, CPACR
91 bic r0, r0, #ASEDIS_BIT
92 bic r0, r0, #TRCDIS_BIT
93 orr r0, r0, #CPACR_ENABLE_FP_ACCESS
94 stcopr r0, CPACR
95 isb
96
97 vmrs r0, FPEXC
98 orr r0, r0, #FPEXC_EN_BIT
99 vmsr FPEXC, r0
100 isb
101 .endm
102
103/* -----------------------------------------------------------------------------
104 * This is the super set of actions that need to be performed during a cold boot
105 * or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN).
106 *
107 * This macro will always perform reset handling, architectural initialisations
108 * and stack setup. The rest of the actions are optional because they might not
109 * be needed, depending on the context in which this macro is called. This is
110 * why this macro is parameterised ; each parameter allows to enable/disable
111 * some actions.
112 *
113 * _set_endian:
114 * Whether the macro needs to configure the endianness of data accesses.
115 *
116 * _warm_boot_mailbox:
117 * Whether the macro needs to detect the type of boot (cold/warm). The
118 * detection is based on the platform entrypoint address : if it is zero
119 * then it is a cold boot, otherwise it is a warm boot. In the latter case,
120 * this macro jumps on the platform entrypoint address.
121 *
122 * _secondary_cold_boot:
123 * Whether the macro needs to identify the CPU that is calling it: primary
124 * CPU or secondary CPU. The primary CPU will be allowed to carry on with
125 * the platform initialisations, while the secondaries will be put in a
126 * platform-specific state in the meantime.
127 *
128 * If the caller knows this macro will only be called by the primary CPU
129 * then this parameter can be defined to 0 to skip this step.
130 *
131 * _init_memory:
132 * Whether the macro needs to initialise the memory.
133 *
134 * _init_c_runtime:
135 * Whether the macro needs to initialise the C runtime environment.
136 *
137 * _exception_vectors:
138 * Address of the exception vectors to program in the VBAR_EL3 register.
139 * -----------------------------------------------------------------------------
140 */
141 .macro el3_entrypoint_common \
142 _set_endian, _warm_boot_mailbox, _secondary_cold_boot, \
143 _init_memory, _init_c_runtime, _exception_vectors
144
145 /* Make sure we are in Secure Mode */
146#if ASM_ASSERTION
147 ldcopr r0, SCR
148 tst r0, #SCR_NS_BIT
149 ASM_ASSERT(eq)
150#endif
151
152 .if \_set_endian
153 /* -------------------------------------------------------------
154 * Set the CPU endianness before doing anything that might
155 * involve memory reads or writes.
156 * -------------------------------------------------------------
157 */
158 ldcopr r0, SCTLR
159 bic r0, r0, #SCTLR_EE_BIT
160 stcopr r0, SCTLR
161 isb
162 .endif /* _set_endian */
163
164 /* Switch to monitor mode */
165 cps #MODE32_mon
166 isb
167
168 .if \_warm_boot_mailbox
169 /* -------------------------------------------------------------
170 * This code will be executed for both warm and cold resets.
171 * Now is the time to distinguish between the two.
172 * Query the platform entrypoint address and if it is not zero
173 * then it means it is a warm boot so jump to this address.
174 * -------------------------------------------------------------
175 */
176 bl plat_get_my_entrypoint
177 cmp r0, #0
178 bxne r0
179 .endif /* _warm_boot_mailbox */
180
181 /* ---------------------------------------------------------------------
182 * It is a cold boot.
183 * Perform any processor specific actions upon reset e.g. cache, TLB
184 * invalidations etc.
185 * ---------------------------------------------------------------------
186 */
187 bl reset_handler
188
189 el3_arch_init_common \_exception_vectors
190
191 .if \_secondary_cold_boot
192 /* -------------------------------------------------------------
193 * Check if this is a primary or secondary CPU cold boot.
194 * The primary CPU will set up the platform while the
195 * secondaries are placed in a platform-specific state until the
196 * primary CPU performs the necessary actions to bring them out
197 * of that state and allows entry into the OS.
198 * -------------------------------------------------------------
199 */
200 bl plat_is_my_cpu_primary
201 cmp r0, #0
202 bne do_primary_cold_boot
203
204 /* This is a cold boot on a secondary CPU */
205 bl plat_secondary_cold_boot_setup
206 /* plat_secondary_cold_boot_setup() is not supposed to return */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000207 no_ret plat_panic_handler
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100208
209 do_primary_cold_boot:
210 .endif /* _secondary_cold_boot */
211
212 /* ---------------------------------------------------------------------
213 * Initialize memory now. Secondary CPU initialization won't get to this
214 * point.
215 * ---------------------------------------------------------------------
216 */
217
218 .if \_init_memory
219 bl platform_mem_init
220 .endif /* _init_memory */
221
222 /* ---------------------------------------------------------------------
223 * Init C runtime environment:
224 * - Zero-initialise the NOBITS sections. There are 2 of them:
225 * - the .bss section;
226 * - the coherent memory section (if any).
227 * - Relocate the data section from ROM to RAM, if required.
228 * ---------------------------------------------------------------------
229 */
230 .if \_init_c_runtime
231#if IMAGE_BL32
232 /* -----------------------------------------------------------------
233 * Invalidate the RW memory used by the BL32 (SP_MIN) image. This
234 * includes the data and NOBITS sections. This is done to
235 * safeguard against possible corruption of this memory by
236 * dirty cache lines in a system cache as a result of use by
237 * an earlier boot loader stage.
238 * -----------------------------------------------------------------
239 */
240 ldr r0, =__RW_START__
241 ldr r1, =__RW_END__
242 sub r1, r1, r0
243 bl inv_dcache_range
244#endif /* IMAGE_BL32 */
245
246 ldr r0, =__BSS_START__
247 ldr r1, =__BSS_SIZE__
248 bl zeromem
249
250#if USE_COHERENT_MEM
251 ldr r0, =__COHERENT_RAM_START__
252 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
253 bl zeromem
254#endif
255
256#if IMAGE_BL1
257 /* -----------------------------------------------------
258 * Copy data from ROM to RAM.
259 * -----------------------------------------------------
260 */
261 ldr r0, =__DATA_RAM_START__
262 ldr r1, =__DATA_ROM_START__
263 ldr r2, =__DATA_SIZE__
Yatharth Kocharc44c5af2016-09-28 11:00:05 +0100264 bl memcpy4
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100265#endif
266 .endif /* _init_c_runtime */
267
268 /* ---------------------------------------------------------------------
269 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
270 * the MMU is enabled. There is no risk of reading stale stack memory
271 * after enabling the MMU as only the primary CPU is running at the
272 * moment.
273 * ---------------------------------------------------------------------
274 */
275 bl plat_set_my_stack
276 .endm
277
278#endif /* __EL3_COMMON_MACROS_S__ */