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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleyea596682015-04-01 17:34:24 +01002 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
Dan Handleyea596682015-04-01 17:34:24 +010030#ifndef __CPU_MACROS_S__
31#define __CPU_MACROS_S__
Achin Gupta4f6ad662013-10-25 09:08:21 +010032
33#include <arch.h>
34
Soby Mathewc704cbc2014-08-14 11:33:56 +010035#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
36 (MIDR_PN_MASK << MIDR_PN_SHIFT)
Achin Gupta4f6ad662013-10-25 09:08:21 +010037
Soby Mathewc704cbc2014-08-14 11:33:56 +010038 /*
39 * Define the offsets to the fields in cpu_ops structure.
40 */
41 .struct 0
42CPU_MIDR: /* cpu_ops midr */
43 .space 8
44/* Reset fn is needed in BL at reset vector */
Yatharth Kochar36433d12014-11-20 18:09:41 +000045#if IMAGE_BL1 || IMAGE_BL31
Soby Mathewc704cbc2014-08-14 11:33:56 +010046CPU_RESET_FUNC: /* cpu_ops reset_func */
47 .space 8
48#endif
Soby Mathew8e2f2872014-08-14 12:49:05 +010049#if IMAGE_BL31 /* The power down core and cluster is needed only in BL3-1 */
50CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */
51 .space 8
52CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */
53 .space 8
54#endif
Soby Mathew38b4bc92014-08-14 13:36:41 +010055#if (IMAGE_BL31 && CRASH_REPORTING)
56CPU_REG_DUMP: /* cpu specific register dump for crash reporting */
57 .space 8
58#endif
Soby Mathewc704cbc2014-08-14 11:33:56 +010059CPU_OPS_SIZE = .
Achin Gupta4f6ad662013-10-25 09:08:21 +010060
Soby Mathewc704cbc2014-08-14 11:33:56 +010061 /*
62 * Convenience macro to declare cpu_ops structure.
63 * Make sure the structure fields are as per the offsets
64 * defined above.
Achin Gupta4f6ad662013-10-25 09:08:21 +010065 */
Soby Mathewc704cbc2014-08-14 11:33:56 +010066 .macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0
67 .section cpu_ops, "a"; .align 3
68 .type cpu_ops_\_name, %object
69 .quad \_midr
Yatharth Kochar36433d12014-11-20 18:09:41 +000070#if IMAGE_BL1 || IMAGE_BL31
Soby Mathewc704cbc2014-08-14 11:33:56 +010071 .if \_noresetfunc
72 .quad 0
73 .else
74 .quad \_name\()_reset_func
75 .endif
76#endif
Soby Mathew8e2f2872014-08-14 12:49:05 +010077#if IMAGE_BL31
78 .quad \_name\()_core_pwr_dwn
79 .quad \_name\()_cluster_pwr_dwn
80#endif
Soby Mathew38b4bc92014-08-14 13:36:41 +010081#if (IMAGE_BL31 && CRASH_REPORTING)
82 .quad \_name\()_cpu_reg_dump
83#endif
Soby Mathewc704cbc2014-08-14 11:33:56 +010084 .endm
Dan Handleyea596682015-04-01 17:34:24 +010085
86#endif /* __CPU_MACROS_S__ */