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Varun Wadekar28dcc212016-07-20 10:28:51 -07001/*
Manish V Badarkhe1af10a22020-07-24 02:05:24 +01002 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
Varun Wadekar3923f882020-05-12 14:04:10 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar28dcc212016-07-20 10:28:51 -07004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar28dcc212016-07-20 10:28:51 -07006 */
7
8#include <arch_helpers.h>
Anthony Zhou70262ef2017-03-22 14:37:04 +08009#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/mmio.h>
Manish V Badarkhe1af10a22020-07-24 02:05:24 +010011#include <lib/smccc.h>
12#include <services/arm_arch_svc.h>
Varun Wadekar28dcc212016-07-20 10:28:51 -070013#include <tegra_def.h>
14#include <tegra_platform.h>
15#include <tegra_private.h>
16
17/*******************************************************************************
18 * Tegra platforms
19 ******************************************************************************/
20typedef enum tegra_platform {
Anthony Zhou4408e882017-07-07 14:29:51 +080021 TEGRA_PLATFORM_SILICON = 0U,
Varun Wadekar28dcc212016-07-20 10:28:51 -070022 TEGRA_PLATFORM_QT,
23 TEGRA_PLATFORM_FPGA,
24 TEGRA_PLATFORM_EMULATION,
Anthony Zhou70262ef2017-03-22 14:37:04 +080025 TEGRA_PLATFORM_LINSIM,
26 TEGRA_PLATFORM_UNIT_FPGA,
27 TEGRA_PLATFORM_VIRT_DEV_KIT,
Varun Wadekar28dcc212016-07-20 10:28:51 -070028 TEGRA_PLATFORM_MAX,
29} tegra_platform_t;
30
31/*******************************************************************************
32 * Tegra macros defining all the SoC minor versions
33 ******************************************************************************/
Anthony Zhou70262ef2017-03-22 14:37:04 +080034#define TEGRA_MINOR_QT U(0)
35#define TEGRA_MINOR_FPGA U(1)
36#define TEGRA_MINOR_ASIM_QT U(2)
37#define TEGRA_MINOR_ASIM_LINSIM U(3)
38#define TEGRA_MINOR_DSIM_ASIM_LINSIM U(4)
39#define TEGRA_MINOR_UNIT_FPGA U(5)
40#define TEGRA_MINOR_VIRT_DEV_KIT U(6)
Varun Wadekar28dcc212016-07-20 10:28:51 -070041
42/*******************************************************************************
Anthony Zhou70262ef2017-03-22 14:37:04 +080043 * Tegra macros defining all the SoC pre_si_platform
44 ******************************************************************************/
45#define TEGRA_PRE_SI_QT U(1)
46#define TEGRA_PRE_SI_FPGA U(2)
47#define TEGRA_PRE_SI_UNIT_FPGA U(3)
48#define TEGRA_PRE_SI_ASIM_QT U(4)
49#define TEGRA_PRE_SI_ASIM_LINSIM U(5)
50#define TEGRA_PRE_SI_DSIM_ASIM_LINSIM U(6)
51#define TEGRA_PRE_SI_VDK U(8)
Varun Wadekar28dcc212016-07-20 10:28:51 -070052
Varun Wadekar28dcc212016-07-20 10:28:51 -070053/*
54 * Read the chip ID value
55 */
56static uint32_t tegra_get_chipid(void)
57{
58 return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET);
59}
60
61/*
62 * Read the chip's major version from chip ID value
63 */
Varun Wadekarfc9b91e2017-03-10 09:53:37 -080064uint32_t tegra_get_chipid_major(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -070065{
66 return (tegra_get_chipid() >> MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK;
67}
68
69/*
70 * Read the chip's minor version from the chip ID value
71 */
Varun Wadekarfc9b91e2017-03-10 09:53:37 -080072uint32_t tegra_get_chipid_minor(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -070073{
74 return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK;
75}
76
Marvin Hsu589a7e12017-04-12 20:40:27 +080077/*
78 * Read the chip's pre_si_platform valus from the chip ID value
79 */
80static uint32_t tegra_get_chipid_pre_si_platform(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -070081{
Marvin Hsu589a7e12017-04-12 20:40:27 +080082 return (tegra_get_chipid() >> PRE_SI_PLATFORM_SHIFT) & PRE_SI_PLATFORM_MASK;
83}
Varun Wadekar28dcc212016-07-20 10:28:51 -070084
Marvin Hsu589a7e12017-04-12 20:40:27 +080085bool tegra_chipid_is_t132(void)
86{
87 uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
88
Anthony Zhou4408e882017-07-07 14:29:51 +080089 return (chip_id == TEGRA_CHIPID_TEGRA13);
Varun Wadekar28dcc212016-07-20 10:28:51 -070090}
91
Marvin Hsu589a7e12017-04-12 20:40:27 +080092bool tegra_chipid_is_t186(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -070093{
94 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
95
Marvin Hsu589a7e12017-04-12 20:40:27 +080096 return (chip_id == TEGRA_CHIPID_TEGRA18);
Varun Wadekar28dcc212016-07-20 10:28:51 -070097}
98
Marvin Hsu589a7e12017-04-12 20:40:27 +080099bool tegra_chipid_is_t210(void)
Varun Wadekarfdcdfe22017-04-13 14:12:49 -0700100{
101 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
102
Anthony Zhou4408e882017-07-07 14:29:51 +0800103 return (chip_id == TEGRA_CHIPID_TEGRA21);
Varun Wadekarfdcdfe22017-04-13 14:12:49 -0700104}
105
Marvin Hsu589a7e12017-04-12 20:40:27 +0800106bool tegra_chipid_is_t210_b01(void)
Anthony Zhou70262ef2017-03-22 14:37:04 +0800107{
Anthony Zhou4408e882017-07-07 14:29:51 +0800108 return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2U));
Anthony Zhou70262ef2017-03-22 14:37:04 +0800109}
110
David Pu819975f2019-08-05 17:00:31 -0700111bool tegra_chipid_is_t194(void)
112{
113 uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
114
115 return (chip_id == TEGRA_CHIPID_TEGRA19);
116}
117
Anthony Zhou70262ef2017-03-22 14:37:04 +0800118/*
Varun Wadekar28dcc212016-07-20 10:28:51 -0700119 * Read the chip ID value and derive the platform
120 */
121static tegra_platform_t tegra_get_platform(void)
122{
Anthony Zhou70262ef2017-03-22 14:37:04 +0800123 uint32_t major, minor, pre_si_platform;
124 tegra_platform_t ret;
125
126 /* get the major/minor chip ID values */
127 major = tegra_get_chipid_major();
128 minor = tegra_get_chipid_minor();
129 pre_si_platform = tegra_get_chipid_pre_si_platform();
130
131 if (major == 0U) {
132 /*
133 * The minor version number is used by simulation platforms
134 */
135 switch (minor) {
136 /*
137 * Cadence's QuickTurn emulation system is a Solaris-based
138 * chip emulation system
139 */
140 case TEGRA_MINOR_QT:
141 case TEGRA_MINOR_ASIM_QT:
142 ret = TEGRA_PLATFORM_QT;
143 break;
144
145 /*
146 * FPGAs are used during early software/hardware development
147 */
148 case TEGRA_MINOR_FPGA:
149 ret = TEGRA_PLATFORM_FPGA;
150 break;
151 /*
152 * Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel
153 * simulation framework.
154 */
155 case TEGRA_MINOR_ASIM_LINSIM:
156 case TEGRA_MINOR_DSIM_ASIM_LINSIM:
157 ret = TEGRA_PLATFORM_LINSIM;
158 break;
Varun Wadekar28dcc212016-07-20 10:28:51 -0700159
Anthony Zhou70262ef2017-03-22 14:37:04 +0800160 /*
161 * Unit FPGAs run the actual hardware block IP on the FPGA with
162 * the other parts of the system using Linsim.
163 */
164 case TEGRA_MINOR_UNIT_FPGA:
165 ret = TEGRA_PLATFORM_UNIT_FPGA;
166 break;
167 /*
168 * The Virtualizer Development Kit (VDK) is the standard chip
169 * development from Synopsis.
170 */
171 case TEGRA_MINOR_VIRT_DEV_KIT:
172 ret = TEGRA_PLATFORM_VIRT_DEV_KIT;
173 break;
Marvin Hsu589a7e12017-04-12 20:40:27 +0800174
Anthony Zhou70262ef2017-03-22 14:37:04 +0800175 default:
Anthony Zhou70262ef2017-03-22 14:37:04 +0800176 ret = TEGRA_PLATFORM_MAX;
177 break;
178 }
Varun Wadekar28dcc212016-07-20 10:28:51 -0700179
Anthony Zhou70262ef2017-03-22 14:37:04 +0800180 } else if (pre_si_platform > 0U) {
Varun Wadekar28dcc212016-07-20 10:28:51 -0700181
Anthony Zhou70262ef2017-03-22 14:37:04 +0800182 switch (pre_si_platform) {
183 /*
184 * Cadence's QuickTurn emulation system is a Solaris-based
185 * chip emulation system
186 */
187 case TEGRA_PRE_SI_QT:
188 case TEGRA_PRE_SI_ASIM_QT:
189 ret = TEGRA_PLATFORM_QT;
190 break;
Varun Wadekar28dcc212016-07-20 10:28:51 -0700191
Anthony Zhou70262ef2017-03-22 14:37:04 +0800192 /*
193 * FPGAs are used during early software/hardware development
194 */
195 case TEGRA_PRE_SI_FPGA:
196 ret = TEGRA_PLATFORM_FPGA;
197 break;
198 /*
199 * Linsim is a reconfigurable, clock-driven, mixed RTL/cmodel
200 * simulation framework.
201 */
202 case TEGRA_PRE_SI_ASIM_LINSIM:
203 case TEGRA_PRE_SI_DSIM_ASIM_LINSIM:
204 ret = TEGRA_PLATFORM_LINSIM;
205 break;
Varun Wadekar28dcc212016-07-20 10:28:51 -0700206
Anthony Zhou70262ef2017-03-22 14:37:04 +0800207 /*
208 * Unit FPGAs run the actual hardware block IP on the FPGA with
209 * the other parts of the system using Linsim.
210 */
211 case TEGRA_PRE_SI_UNIT_FPGA:
212 ret = TEGRA_PLATFORM_UNIT_FPGA;
213 break;
214 /*
215 * The Virtualizer Development Kit (VDK) is the standard chip
216 * development from Synopsis.
217 */
218 case TEGRA_PRE_SI_VDK:
219 ret = TEGRA_PLATFORM_VIRT_DEV_KIT;
220 break;
Varun Wadekar28dcc212016-07-20 10:28:51 -0700221
Anthony Zhou70262ef2017-03-22 14:37:04 +0800222 default:
Anthony Zhou70262ef2017-03-22 14:37:04 +0800223 ret = TEGRA_PLATFORM_MAX;
224 break;
225 }
226
227 } else {
228 /* Actual silicon platforms have a non-zero major version */
229 ret = TEGRA_PLATFORM_SILICON;
230 }
231
232 return ret;
233}
234
235bool tegra_platform_is_silicon(void)
236{
237 return ((tegra_get_platform() == TEGRA_PLATFORM_SILICON) ? true : false);
Varun Wadekar28dcc212016-07-20 10:28:51 -0700238}
239
Anthony Zhou70262ef2017-03-22 14:37:04 +0800240bool tegra_platform_is_qt(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700241{
Anthony Zhou70262ef2017-03-22 14:37:04 +0800242 return ((tegra_get_platform() == TEGRA_PLATFORM_QT) ? true : false);
Varun Wadekar28dcc212016-07-20 10:28:51 -0700243}
244
Anthony Zhou70262ef2017-03-22 14:37:04 +0800245bool tegra_platform_is_linsim(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700246{
Anthony Zhou70262ef2017-03-22 14:37:04 +0800247 tegra_platform_t plat = tegra_get_platform();
248
249 return (((plat == TEGRA_PLATFORM_LINSIM) ||
250 (plat == TEGRA_PLATFORM_UNIT_FPGA)) ? true : false);
Varun Wadekar28dcc212016-07-20 10:28:51 -0700251}
252
Anthony Zhou70262ef2017-03-22 14:37:04 +0800253bool tegra_platform_is_fpga(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700254{
Anthony Zhou70262ef2017-03-22 14:37:04 +0800255 return ((tegra_get_platform() == TEGRA_PLATFORM_FPGA) ? true : false);
Varun Wadekar28dcc212016-07-20 10:28:51 -0700256}
257
Anthony Zhou70262ef2017-03-22 14:37:04 +0800258bool tegra_platform_is_emulation(void)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700259{
260 return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION);
261}
Anthony Zhou70262ef2017-03-22 14:37:04 +0800262
263bool tegra_platform_is_unit_fpga(void)
264{
265 return ((tegra_get_platform() == TEGRA_PLATFORM_UNIT_FPGA) ? true : false);
266}
267
268bool tegra_platform_is_virt_dev_kit(void)
269{
270 return ((tegra_get_platform() == TEGRA_PLATFORM_VIRT_DEV_KIT) ? true : false);
271}
Varun Wadekar3923f882020-05-12 14:04:10 -0700272
273/*
274 * This function returns soc version which mainly consist of below fields
275 *
276 * soc_version[30:24] = JEP-106 continuation code for the SiP
277 * soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
278 * soc_version[0:15] = chip identification
279 */
280int32_t plat_get_soc_version(void)
281{
282 uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
283 uint32_t manfid = (JEDEC_NVIDIA_BKID << 24) | (JEDEC_NVIDIA_MFID << 16);
284
285 return (int32_t)(manfid | (chip_id & 0xFFFF));
286}
287
288/*
289 * This function returns soc revision in below format
290 *
291 * soc_revision[8:15] = major version number
292 * soc_revision[0:7] = minor version number
293 */
294int32_t plat_get_soc_revision(void)
295{
296 return (int32_t)((tegra_get_chipid_major() << 8) | tegra_get_chipid_minor());
297}
Manish V Badarkhe1af10a22020-07-24 02:05:24 +0100298
299/*****************************************************************************
Manish V Badarkheb0fcdbf2020-11-19 19:52:41 +0000300 * plat_is_smccc_feature_available() - This function checks whether SMCCC feature
Manish V Badarkhe1af10a22020-07-24 02:05:24 +0100301 * is availabile for the platform or not.
302 * @fid: SMCCC function id
303 *
304 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
305 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
306 *****************************************************************************/
Manish V Badarkheb0fcdbf2020-11-19 19:52:41 +0000307int32_t plat_is_smccc_feature_available(u_register_t fid)
Manish V Badarkhe1af10a22020-07-24 02:05:24 +0100308{
309 switch (fid) {
310 case SMCCC_ARCH_SOC_ID:
311 return SMC_ARCH_CALL_SUCCESS;
312 default:
313 return SMC_ARCH_CALL_NOT_SUPPORTED;
314 }
315}