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developer65014b82015-04-13 14:47:57 +08001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#ifndef __SPM_H__
31#define __SPM_H__
32
33#define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000)
34#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010)
35#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014)
36#define SPM_CLK_SETTLE (SPM_BASE + 0x100)
37#define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218)
38#define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c)
39#define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220)
40#define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264)
41#define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c)
42#define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274)
43#define SPM_MD32_SRAM_CON (SPM_BASE + 0x2c8)
44#define SPM_PCM_CON0 (SPM_BASE + 0x310)
45#define SPM_PCM_CON1 (SPM_BASE + 0x314)
46#define SPM_PCM_IM_PTR (SPM_BASE + 0x318)
47#define SPM_PCM_IM_LEN (SPM_BASE + 0x31c)
48#define SPM_PCM_REG_DATA_INI (SPM_BASE + 0x320)
49#define SPM_PCM_EVENT_VECTOR0 (SPM_BASE + 0x340)
50#define SPM_PCM_EVENT_VECTOR1 (SPM_BASE + 0x344)
51#define SPM_PCM_EVENT_VECTOR2 (SPM_BASE + 0x348)
52#define SPM_PCM_EVENT_VECTOR3 (SPM_BASE + 0x34c)
53#define SPM_PCM_MAS_PAUSE_MASK (SPM_BASE + 0x354)
54#define SPM_PCM_PWR_IO_EN (SPM_BASE + 0x358)
55#define SPM_PCM_TIMER_VAL (SPM_BASE + 0x35c)
56#define SPM_PCM_TIMER_OUT (SPM_BASE + 0x360)
57#define SPM_PCM_REG0_DATA (SPM_BASE + 0x380)
58#define SPM_PCM_REG1_DATA (SPM_BASE + 0x384)
59#define SPM_PCM_REG2_DATA (SPM_BASE + 0x388)
60#define SPM_PCM_REG3_DATA (SPM_BASE + 0x38c)
61#define SPM_PCM_REG4_DATA (SPM_BASE + 0x390)
62#define SPM_PCM_REG5_DATA (SPM_BASE + 0x394)
63#define SPM_PCM_REG6_DATA (SPM_BASE + 0x398)
64#define SPM_PCM_REG7_DATA (SPM_BASE + 0x39c)
65#define SPM_PCM_REG8_DATA (SPM_BASE + 0x3a0)
66#define SPM_PCM_REG9_DATA (SPM_BASE + 0x3a4)
67#define SPM_PCM_REG10_DATA (SPM_BASE + 0x3a8)
68#define SPM_PCM_REG11_DATA (SPM_BASE + 0x3ac)
69#define SPM_PCM_REG12_DATA (SPM_BASE + 0x3b0)
70#define SPM_PCM_REG13_DATA (SPM_BASE + 0x3b4)
71#define SPM_PCM_REG14_DATA (SPM_BASE + 0x3b8)
72#define SPM_PCM_REG15_DATA (SPM_BASE + 0x3bc)
73#define SPM_PCM_EVENT_REG_STA (SPM_BASE + 0x3c0)
74#define SPM_PCM_FSM_STA (SPM_BASE + 0x3c4)
75#define SPM_PCM_IM_HOST_RW_PTR (SPM_BASE + 0x3c8)
76#define SPM_PCM_IM_HOST_RW_DAT (SPM_BASE + 0x3cc)
77#define SPM_PCM_EVENT_VECTOR4 (SPM_BASE + 0x3d0)
78#define SPM_PCM_EVENT_VECTOR5 (SPM_BASE + 0x3d4)
79#define SPM_PCM_EVENT_VECTOR6 (SPM_BASE + 0x3d8)
80#define SPM_PCM_EVENT_VECTOR7 (SPM_BASE + 0x3dc)
81#define SPM_PCM_SW_INT_SET (SPM_BASE + 0x3e0)
82#define SPM_PCM_SW_INT_CLEAR (SPM_BASE + 0x3e4)
83#define SPM_CLK_CON (SPM_BASE + 0x400)
84#define SPM_SLEEP_PTPOD2_CON (SPM_BASE + 0x408)
85#define SPM_APMCU_PWRCTL (SPM_BASE + 0x600)
86#define SPM_AP_DVFS_CON_SET (SPM_BASE + 0x604)
87#define SPM_AP_STANBY_CON (SPM_BASE + 0x608)
88#define SPM_PWR_STATUS (SPM_BASE + 0x60c)
89#define SPM_PWR_STATUS_2ND (SPM_BASE + 0x610)
90#define SPM_AP_BSI_REQ (SPM_BASE + 0x614)
91#define SPM_SLEEP_TIMER_STA (SPM_BASE + 0x720)
92#define SPM_SLEEP_WAKEUP_EVENT_MASK (SPM_BASE + 0x810)
93#define SPM_SLEEP_CPU_WAKEUP_EVENT (SPM_BASE + 0x814)
94#define SPM_SLEEP_MD32_WAKEUP_EVENT_MASK (SPM_BASE + 0x818)
95#define SPM_PCM_WDT_TIMER_VAL (SPM_BASE + 0x824)
96#define SPM_PCM_WDT_TIMER_OUT (SPM_BASE + 0x828)
97#define SPM_PCM_MD32_MAILBOX (SPM_BASE + 0x830)
98#define SPM_PCM_MD32_IRQ (SPM_BASE + 0x834)
99#define SPM_SLEEP_ISR_MASK (SPM_BASE + 0x900)
100#define SPM_SLEEP_ISR_STATUS (SPM_BASE + 0x904)
101#define SPM_SLEEP_ISR_RAW_STA (SPM_BASE + 0x910)
102#define SPM_SLEEP_MD32_ISR_RAW_STA (SPM_BASE + 0x914)
103#define SPM_SLEEP_WAKEUP_MISC (SPM_BASE + 0x918)
104#define SPM_SLEEP_BUS_PROTECT_RDY (SPM_BASE + 0x91c)
105#define SPM_SLEEP_SUBSYS_IDLE_STA (SPM_BASE + 0x920)
106#define SPM_PCM_RESERVE (SPM_BASE + 0xb00)
107#define SPM_PCM_RESERVE2 (SPM_BASE + 0xb04)
108#define SPM_PCM_FLAGS (SPM_BASE + 0xb08)
109#define SPM_PCM_SRC_REQ (SPM_BASE + 0xb0c)
110#define SPM_PCM_DEBUG_CON (SPM_BASE + 0xb20)
111#define SPM_CA7_CPU0_IRQ_MASK (SPM_BASE + 0xb30)
112#define SPM_CA7_CPU1_IRQ_MASK (SPM_BASE + 0xb34)
113#define SPM_CA7_CPU2_IRQ_MASK (SPM_BASE + 0xb38)
114#define SPM_CA7_CPU3_IRQ_MASK (SPM_BASE + 0xb3c)
115#define SPM_CA15_CPU0_IRQ_MASK (SPM_BASE + 0xb40)
116#define SPM_CA15_CPU1_IRQ_MASK (SPM_BASE + 0xb44)
117#define SPM_CA15_CPU2_IRQ_MASK (SPM_BASE + 0xb48)
118#define SPM_CA15_CPU3_IRQ_MASK (SPM_BASE + 0xb4c)
119#define SPM_PCM_PASR_DPD_0 (SPM_BASE + 0xb60)
120#define SPM_PCM_PASR_DPD_1 (SPM_BASE + 0xb64)
121#define SPM_PCM_PASR_DPD_2 (SPM_BASE + 0xb68)
122#define SPM_PCM_PASR_DPD_3 (SPM_BASE + 0xb6c)
123#define SPM_SLEEP_CA7_WFI0_EN (SPM_BASE + 0xf00)
124#define SPM_SLEEP_CA7_WFI1_EN (SPM_BASE + 0xf04)
125#define SPM_SLEEP_CA7_WFI2_EN (SPM_BASE + 0xf08)
126#define SPM_SLEEP_CA7_WFI3_EN (SPM_BASE + 0xf0c)
127#define SPM_SLEEP_CA15_WFI0_EN (SPM_BASE + 0xf10)
128#define SPM_SLEEP_CA15_WFI1_EN (SPM_BASE + 0xf14)
129#define SPM_SLEEP_CA15_WFI2_EN (SPM_BASE + 0xf18)
130#define SPM_SLEEP_CA15_WFI3_EN (SPM_BASE + 0xf1c)
131
developer512a3112015-11-16 14:26:14 +0800132#define AP_PLL_CON3 0x1020900c
133#define AP_PLL_CON4 0x10209010
134
developer65014b82015-04-13 14:47:57 +0800135#define SPM_PROJECT_CODE 0xb16
136
137#define SPM_REGWR_EN (1U << 0)
138#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
139
140#define SPM_CPU_PDN_DIS (1U << 0)
141#define SPM_INFRA_PDN_DIS (1U << 1)
142#define SPM_DDRPHY_PDN_DIS (1U << 2)
143#define SPM_DUALVCORE_PDN_DIS (1U << 3)
144#define SPM_PASR_DIS (1U << 4)
145#define SPM_DPD_DIS (1U << 5)
146#define SPM_SODI_DIS (1U << 6)
147#define SPM_MEMPLL_RESET (1U << 7)
148#define SPM_MAINPLL_PDN_DIS (1U << 8)
149#define SPM_CPU_DVS_DIS (1U << 9)
150#define SPM_CPU_DORMANT (1U << 10)
151#define SPM_EXT_VSEL_GPIO103 (1U << 11)
152#define SPM_DDR_HIGH_SPEED (1U << 12)
153#define SPM_OPT (1U << 13)
154
155#define POWER_ON_VAL1_DEF 0x01011820
156#define PCM_FSM_STA_DEF 0x48490
157#define PCM_END_FSM_STA_DEF 0x08490
158#define PCM_END_FSM_STA_MASK 0x3fff0
159#define PCM_HANDSHAKE_SEND1 0xbeefbeef
160
161#define PCM_WDT_TIMEOUT (30 * 32768)
162#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
163
164#define CON0_PCM_KICK (1U << 0)
165#define CON0_IM_KICK (1U << 1)
166#define CON0_IM_SLEEP_DVS (1U << 3)
167#define CON0_PCM_SW_RESET (1U << 15)
168#define CON0_CFG_KEY (SPM_PROJECT_CODE << 16)
169
170#define CON1_IM_SLAVE (1U << 0)
171#define CON1_MIF_APBEN (1U << 3)
172#define CON1_PCM_TIMER_EN (1U << 5)
173#define CON1_IM_NONRP_EN (1U << 6)
174#define CON1_PCM_WDT_EN (1U << 8)
175#define CON1_PCM_WDT_WAKE_MODE (1U << 9)
176#define CON1_SPM_SRAM_SLP_B (1U << 10)
177#define CON1_SPM_SRAM_ISO_B (1U << 11)
178#define CON1_EVENT_LOCK_EN (1U << 12)
179#define CON1_CFG_KEY (SPM_PROJECT_CODE << 16)
180
181#define PCM_PWRIO_EN_R0 (1U << 0)
182#define PCM_PWRIO_EN_R7 (1U << 7)
183#define PCM_RF_SYNC_R0 (1U << 16)
184#define PCM_RF_SYNC_R2 (1U << 18)
185#define PCM_RF_SYNC_R6 (1U << 22)
186#define PCM_RF_SYNC_R7 (1U << 23)
187
188#define CC_SYSCLK0_EN_0 (1U << 0)
189#define CC_SYSCLK0_EN_1 (1U << 1)
190#define CC_SYSCLK1_EN_0 (1U << 2)
191#define CC_SYSCLK1_EN_1 (1U << 3)
192#define CC_SYSSETTLE_SEL (1U << 4)
193#define CC_LOCK_INFRA_DCM (1U << 5)
194#define CC_SRCLKENA_MASK_0 (1U << 6)
195#define CC_CXO32K_RM_EN_MD1 (1U << 9)
196#define CC_CXO32K_RM_EN_MD2 (1U << 10)
197#define CC_CLKSQ1_SEL (1U << 12)
198#define CC_DISABLE_DORM_PWR (1U << 14)
199#define CC_MD32_DCM_EN (1U << 18)
200
201#define WFI_OP_AND 1
202#define WFI_OP_OR 0
203
204#define WAKE_MISC_PCM_TIMER (1U << 19)
205#define WAKE_MISC_CPU_WAKE (1U << 20)
206
207/* define WAKE_SRC_XXX */
208#define WAKE_SRC_SPM_MERGE (1 << 0)
209#define WAKE_SRC_KP (1 << 2)
210#define WAKE_SRC_WDT (1 << 3)
211#define WAKE_SRC_GPT (1 << 4)
212#define WAKE_SRC_EINT (1 << 6)
213#define WAKE_SRC_LOW_BAT (1 << 9)
214#define WAKE_SRC_MD32 (1 << 10)
215#define WAKE_SRC_USB_CD (1 << 14)
216#define WAKE_SRC_USB_PDN (1 << 15)
217#define WAKE_SRC_AFE (1 << 20)
218#define WAKE_SRC_THERM (1 << 21)
219#define WAKE_SRC_SYSPWREQ (1 << 24)
220#define WAKE_SRC_SEJ (1 << 27)
221#define WAKE_SRC_ALL_MD32 (1 << 28)
222#define WAKE_SRC_CPU_IRQ (1 << 29)
223
224enum wake_reason_t {
225 WR_NONE = 0,
226 WR_UART_BUSY = 1,
227 WR_PCM_ASSERT = 2,
228 WR_PCM_TIMER = 3,
229 WR_PCM_ABORT = 4,
230 WR_WAKE_SRC = 5,
231 WR_UNKNOWN = 6,
232};
233
234struct pwr_ctrl {
235 unsigned int pcm_flags;
236 unsigned int pcm_flags_cust;
237 unsigned int pcm_reserve;
238 unsigned int timer_val;
239 unsigned int timer_val_cust;
240 unsigned int wake_src;
241 unsigned int wake_src_cust;
242 unsigned int wake_src_md32;
243 unsigned short r0_ctrl_en;
244 unsigned short r7_ctrl_en;
245 unsigned short infra_dcm_lock;
246 unsigned short pcm_apsrc_req;
247 unsigned short mcusys_idle_mask;
248 unsigned short ca15top_idle_mask;
249 unsigned short ca7top_idle_mask;
250 unsigned short wfi_op;
251 unsigned short ca15_wfi0_en;
252 unsigned short ca15_wfi1_en;
253 unsigned short ca15_wfi2_en;
254 unsigned short ca15_wfi3_en;
255 unsigned short ca7_wfi0_en;
256 unsigned short ca7_wfi1_en;
257 unsigned short ca7_wfi2_en;
258 unsigned short ca7_wfi3_en;
259 unsigned short disp_req_mask;
260 unsigned short mfg_req_mask;
261 unsigned short md32_req_mask;
262 unsigned short syspwreq_mask;
263 unsigned short srclkenai_mask;
264};
265
266struct wake_status {
267 unsigned int assert_pc;
268 unsigned int r12;
269 unsigned int raw_sta;
270 unsigned int wake_misc;
271 unsigned int timer_out;
272 unsigned int r13;
273 unsigned int idle_sta;
274 unsigned int debug_flag;
275 unsigned int event_reg;
276 unsigned int isr;
277};
278
279struct pcm_desc {
280 const char *version; /* PCM code version */
281 const unsigned int *base; /* binary array base */
282 const unsigned int size; /* binary array size */
283 const unsigned char sess; /* session number */
284 const unsigned char replace; /* replace mode */
285
286 unsigned int vec0; /* event vector 0 config */
287 unsigned int vec1; /* event vector 1 config */
288 unsigned int vec2; /* event vector 2 config */
289 unsigned int vec3; /* event vector 3 config */
290 unsigned int vec4; /* event vector 4 config */
291 unsigned int vec5; /* event vector 5 config */
292 unsigned int vec6; /* event vector 6 config */
293 unsigned int vec7; /* event vector 7 config */
294};
295
296struct spm_lp_scen {
297 const struct pcm_desc *pcmdesc;
298 struct pwr_ctrl *pwrctrl;
299};
300
301#define EVENT_VEC(event, resume, imme, pc) \
302 (((pc) << 16) | \
303 (!!(imme) << 6) | \
304 (!!(resume) << 5) | \
305 ((event) & 0x1f))
306
307#define spm_read(addr) mmio_read_32(addr)
308#define spm_write(addr, val) mmio_write_32(addr, val)
309
310#define is_cpu_pdn(flags) (!((flags) & SPM_CPU_PDN_DIS))
311#define is_infra_pdn(flags) (!((flags) & SPM_INFRA_PDN_DIS))
312#define is_ddrphy_pdn(flags) (!((flags) & SPM_DDRPHY_PDN_DIS))
313
314static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
315 unsigned int flags)
316{
317 flags &= ~SPM_EXT_VSEL_GPIO103;
318
319 if (pwrctrl->pcm_flags_cust == 0)
320 pwrctrl->pcm_flags = flags;
321 else
322 pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
323}
324
325static inline void set_pwrctrl_pcm_data(struct pwr_ctrl *pwrctrl,
326 unsigned int data)
327{
328 pwrctrl->pcm_reserve = data;
329}
330
331void spm_reset_and_init_pcm(void);
332
333void spm_init_pcm_register(void); /* init r0 and r7 */
334void spm_set_power_control(const struct pwr_ctrl *pwrctrl);
335void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
336
337void spm_get_wakeup_status(struct wake_status *wakesta);
338void spm_set_sysclk_settle(void);
339void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
340void spm_clean_after_wakeup(void);
341enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta);
342void spm_register_init(void);
343void spm_go_to_hotplug(void);
344void spm_init_event_vector(const struct pcm_desc *pcmdesc);
345void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
346void spm_set_sysclk_settle(void);
347int is_mcdi_ready(void);
348int is_hotplug_ready(void);
349int is_suspend_ready(void);
350void set_mcdi_ready(void);
351void set_hotplug_ready(void);
352void set_suspend_ready(void);
353void clear_all_ready(void);
354void spm_lock_init(void);
355void spm_lock_get(void);
356void spm_lock_release(void);
357void spm_boot_init(void);
358
359#endif /* __SPM_H__ */