| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <plat/common/common_def.h> |
| 10 | #include <memctrl_v2.h> |
| 11 | #include <tegra_def.h> |
| 12 | |
| Stefan Kristiansson | fa871a6 | 2017-03-20 14:19:46 +0200 | [diff] [blame] | 13 | #define TEGRA186_SMMU_CTX_SIZE 0x490 |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 14 | |
| 15 | .align 4 |
| 16 | .globl tegra186_cpu_reset_handler |
| 17 | |
| 18 | /* CPU reset handler routine */ |
| 19 | func tegra186_cpu_reset_handler |
| 20 | /* |
| 21 | * The TZRAM loses state during System Suspend. We use this |
| 22 | * information to decide if the reset handler is running after a |
| 23 | * System Suspend. Resume from system suspend requires restoring |
| 24 | * the entire state from TZDRAM to TZRAM. |
| 25 | */ |
| 26 | mov x0, #BL31_BASE |
| 27 | ldr x0, [x0] |
| 28 | cbnz x0, boot_cpu |
| 29 | |
| 30 | /* resume from system suspend */ |
| 31 | mov x0, #BL31_BASE |
| 32 | adr x1, __tegra186_cpu_reset_handler_end |
| 33 | adr x2, __tegra186_cpu_reset_handler_data |
| 34 | ldr x2, [x2, #8] |
| 35 | |
| 36 | /* memcpy16 */ |
| 37 | m_loop16: |
| 38 | cmp x2, #16 |
| 39 | b.lt m_loop1 |
| 40 | ldp x3, x4, [x1], #16 |
| 41 | stp x3, x4, [x0], #16 |
| 42 | sub x2, x2, #16 |
| 43 | b m_loop16 |
| 44 | /* copy byte per byte */ |
| 45 | m_loop1: |
| 46 | cbz x2, boot_cpu |
| 47 | ldrb w3, [x1], #1 |
| 48 | strb w3, [x0], #1 |
| 49 | subs x2, x2, #1 |
| 50 | b.ne m_loop1 |
| 51 | |
| 52 | boot_cpu: |
| 53 | adr x0, __tegra186_cpu_reset_handler_data |
| 54 | ldr x0, [x0] |
| 55 | br x0 |
| 56 | endfunc tegra186_cpu_reset_handler |
| 57 | |
| 58 | /* |
| Stefan Kristiansson | fa871a6 | 2017-03-20 14:19:46 +0200 | [diff] [blame] | 59 | * Tegra186 reset data (offset 0x0 - 0x2490) |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 60 | * |
| Stefan Kristiansson | fa871a6 | 2017-03-20 14:19:46 +0200 | [diff] [blame] | 61 | * 0x0000: secure world's entrypoint |
| 62 | * 0x0008: BL31 size (RO + RW) |
| 63 | * 0x0010: SMMU context start |
| 64 | * 0x2490: SMMU context end |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 65 | */ |
| 66 | |
| 67 | .align 4 |
| 68 | .type __tegra186_cpu_reset_handler_data, %object |
| 69 | .globl __tegra186_cpu_reset_handler_data |
| 70 | __tegra186_cpu_reset_handler_data: |
| 71 | .quad tegra_secure_entrypoint |
| 72 | .quad __BL31_END__ - BL31_BASE |
| 73 | .globl __tegra186_smmu_ctx_start |
| 74 | __tegra186_smmu_ctx_start: |
| 75 | .rept TEGRA186_SMMU_CTX_SIZE |
| 76 | .quad 0 |
| 77 | .endr |
| 78 | .size __tegra186_cpu_reset_handler_data, \ |
| 79 | . - __tegra186_cpu_reset_handler_data |
| 80 | |
| 81 | .align 4 |
| 82 | .globl __tegra186_cpu_reset_handler_end |
| 83 | __tegra186_cpu_reset_handler_end: |