| Haojian Zhuang | 5f281b3 | 2017-05-24 08:45:05 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef HI6220_REGS_PIN_H |
| 8 | #define HI6220_REGS_PIN_H |
| Haojian Zhuang | 5f281b3 | 2017-05-24 08:45:05 +0800 | [diff] [blame] | 9 | |
| 10 | #define IOMG_BASE 0xF7010000 |
| 11 | |
| 12 | #define IOMG_SD_CLK (IOMG_BASE + 0x0C) |
| 13 | #define IOMG_SD_CMD (IOMG_BASE + 0x10) |
| 14 | #define IOMG_SD_DATA0 (IOMG_BASE + 0x14) |
| 15 | #define IOMG_SD_DATA1 (IOMG_BASE + 0x18) |
| 16 | #define IOMG_SD_DATA2 (IOMG_BASE + 0x1C) |
| 17 | #define IOMG_SD_DATA3 (IOMG_BASE + 0x20) |
| 18 | #define IOMG_GPIO24 (IOMG_BASE + 0x140) |
| 19 | |
| 20 | #define IOMG_MUX_FUNC0 0 |
| 21 | #define IOMG_MUX_FUNC1 1 |
| 22 | #define IOMG_MUX_FUNC2 2 |
| 23 | |
| 24 | #define IOCG1_BASE 0xF7010800 |
| 25 | #define IOCG2_BASE 0xF8001800 |
| 26 | |
| 27 | #define IOCG_SD_CLK (IOCG1_BASE + 0x0C) |
| 28 | #define IOCG_SD_CMD (IOCG1_BASE + 0x10) |
| 29 | #define IOCG_SD_DATA0 (IOCG1_BASE + 0x14) |
| 30 | #define IOCG_SD_DATA1 (IOCG1_BASE + 0x18) |
| 31 | #define IOCG_SD_DATA2 (IOCG1_BASE + 0x1C) |
| 32 | #define IOCG_SD_DATA3 (IOCG1_BASE + 0x20) |
| 33 | #define IOCG_GPIO24 (IOCG1_BASE + 0x150) |
| 34 | #define IOCG_GPIO8 (IOCG2_BASE + 0x30) |
| 35 | |
| 36 | #define IOCG_DRIVE_8MA (2 << 4) |
| 37 | #define IOCG_DRIVE_10MA (3 << 4) |
| 38 | #define IOCG_INPUT_16MA 0x64 |
| 39 | #define IOCG_INPUT_12MA 0x54 |
| 40 | #define IOCG_PULLDOWN (1 << 1) |
| 41 | #define IOCG_PULLUP (1 << 0) |
| 42 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 43 | #endif /* HI6220_REGS_PIN_H */ |