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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -07002 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
10#include <arch.h>
Tejas Patel0a2f9ad2018-12-14 00:55:30 -080011#include "versal_def.h"
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053012
13/*******************************************************************************
14 * Generic platform constants
15 ******************************************************************************/
16
17/* Size of cacheable stacks */
18#define PLATFORM_STACK_SIZE 0x440
19
Deepika Bhavnanib16bada2019-12-13 10:53:56 -060020#define PLATFORM_CORE_COUNT U(2)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053021#define PLAT_MAX_PWR_LVL 1
22#define PLAT_MAX_RET_STATE 1
23#define PLAT_MAX_OFF_STATE 2
24
25/*******************************************************************************
26 * BL31 specific defines.
27 ******************************************************************************/
28/*
29 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
30 * present). BL31_BASE is calculated using the current BL31 debug size plus a
31 * little space for growth.
32 */
33#ifndef VERSAL_ATF_MEM_BASE
Venkatesh Yadav Abbarapu5aa76f92019-11-25 01:47:48 -070034# define BL31_BASE 0xfffe0000
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053035# define BL31_LIMIT 0xffffffff
36#else
37# define BL31_BASE (VERSAL_ATF_MEM_BASE)
38# define BL31_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE - 1)
39# ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
40# define BL31_PROGBITS_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_PROGBITS_SIZE - 1)
41# endif
42#endif
43
44/*******************************************************************************
45 * BL32 specific defines.
46 ******************************************************************************/
47#ifndef VERSAL_BL32_MEM_BASE
48# define BL32_BASE 0x60000000
49# define BL32_LIMIT 0x7fffffff
50#else
51# define BL32_BASE (VERSAL_BL32_MEM_BASE)
52# define BL32_LIMIT (VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE - 1)
53#endif
54
55/*******************************************************************************
56 * BL33 specific defines.
57 ******************************************************************************/
58#ifndef PRELOADED_BL33_BASE
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070059# define PLAT_ARM_NS_IMAGE_BASE 0x8000000
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053060#else
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070061# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053062#endif
63
64/*******************************************************************************
65 * TSP specific defines.
66 ******************************************************************************/
67#define TSP_SEC_MEM_BASE BL32_BASE
68#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
69
70/* ID of the secure physical generic timer interrupt used by the TSP */
71#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
72
73/*******************************************************************************
74 * Platform specific page table and MMU setup constants
75 ******************************************************************************/
76#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
77#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
Tejas Patel54d13192019-02-27 18:44:55 +053078#define MAX_MMAP_REGIONS 8
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053079#define MAX_XLAT_TABLES 5
80
81#define CACHE_WRITEBACK_SHIFT 6
82#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
83
84#define PLAT_VERSAL_GICD_BASE 0xF9000000
85#define PLAT_VERSAL_GICR_BASE 0xF9080000
86
87/*
88 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
89 * terminology. On a GICv2 system or mode, the lists will be merged and treated
90 * as Group 0 interrupts.
91 */
92#define PLAT_VERSAL_G1S_IRQS VERSAL_IRQ_SEC_PHY_TIMER
93#define PLAT_VERSAL_G0_IRQS VERSAL_IRQ_SEC_PHY_TIMER
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +053094#define PLAT_VERSAL_IPI_IRQ 62
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053095
96#define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \
97 INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
98 GIC_INTR_CFG_LEVEL)
99
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530100#define PLAT_VERSAL_G0_IRQ_PROPS(grp) \
101 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
102 GIC_INTR_CFG_EDGE), \
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530103
104#endif /* PLATFORM_DEF_H */