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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathewe364a8a2015-04-13 16:57:12 +01002 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
Soby Mathew8e2f2872014-08-14 12:49:05 +01006#include <aem_generic.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01007#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +00008#include <asm_macros.S>
Soby Mathewc704cbc2014-08-14 11:33:56 +01009#include <cpu_macros.S>
10
Soby Mathew8e2f2872014-08-14 12:49:05 +010011func aem_generic_core_pwr_dwn
12 /* ---------------------------------------------
13 * Disable the Data Cache.
14 * ---------------------------------------------
15 */
16 mrs x1, sctlr_el3
17 bic x1, x1, #SCTLR_C_BIT
18 msr sctlr_el3, x1
19 isb
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
Soby Mathew8e2f2872014-08-14 12:49:05 +010021 mov x0, #DCCISW
Achin Gupta4f6ad662013-10-25 09:08:21 +010022
Soby Mathew8e2f2872014-08-14 12:49:05 +010023 /* ---------------------------------------------
24 * Flush L1 cache to PoU.
25 * ---------------------------------------------
26 */
27 b dcsw_op_louis
Kévin Petita877c252015-03-24 14:03:57 +000028endfunc aem_generic_core_pwr_dwn
Achin Gupta4f6ad662013-10-25 09:08:21 +010029
Soby Mathew8e2f2872014-08-14 12:49:05 +010030
31func aem_generic_cluster_pwr_dwn
32 /* ---------------------------------------------
33 * Disable the Data Cache.
34 * ---------------------------------------------
35 */
36 mrs x1, sctlr_el3
37 bic x1, x1, #SCTLR_C_BIT
38 msr sctlr_el3, x1
39 isb
40
41 /* ---------------------------------------------
42 * Flush L1 and L2 caches to PoC.
43 * ---------------------------------------------
44 */
45 mov x0, #DCCISW
46 b dcsw_op_all
Kévin Petita877c252015-03-24 14:03:57 +000047endfunc aem_generic_cluster_pwr_dwn
Soby Mathew8e2f2872014-08-14 12:49:05 +010048
Soby Mathew0980dce2018-09-17 04:34:35 +010049#if REPORT_ERRATA
50/*
51 * Errata printing function for AEM. Must follow AAPCS.
52 */
53func aem_generic_errata_report
54 ret
55endfunc aem_generic_errata_report
56#endif
57
Soby Mathew38b4bc92014-08-14 13:36:41 +010058 /* ---------------------------------------------
59 * This function provides cpu specific
60 * register information for crash reporting.
61 * It needs to return with x6 pointing to
62 * a list of register names in ascii and
63 * x8 - x15 having values of registers to be
64 * reported.
65 * ---------------------------------------------
66 */
Soby Mathewe364a8a2015-04-13 16:57:12 +010067.section .rodata.aem_generic_regs, "aS"
68aem_generic_regs: /* The ascii list of register names to be reported */
69 .asciz "" /* no registers to report */
70
Soby Mathew38b4bc92014-08-14 13:36:41 +010071func aem_generic_cpu_reg_dump
Soby Mathewe364a8a2015-04-13 16:57:12 +010072 adr x6, aem_generic_regs
Soby Mathew38b4bc92014-08-14 13:36:41 +010073 ret
Kévin Petita877c252015-03-24 14:03:57 +000074endfunc aem_generic_cpu_reg_dump
Soby Mathew38b4bc92014-08-14 13:36:41 +010075
Soby Mathew8e2f2872014-08-14 12:49:05 +010076
77/* cpu_ops for Base AEM FVP */
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +000078declare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \
79 aem_generic_core_pwr_dwn, \
80 aem_generic_cluster_pwr_dwn
Soby Mathewc704cbc2014-08-14 11:33:56 +010081
Soby Mathew8e2f2872014-08-14 12:49:05 +010082/* cpu_ops for Foundation FVP */
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +000083declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, CPU_NO_RESET_FUNC, \
84 aem_generic_core_pwr_dwn, \
85 aem_generic_cluster_pwr_dwn