blob: 9fae7e917c92fee1defaff73620571518c237d66 [file] [log] [blame]
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01001/*
Jimmy Brissoned202072020-08-04 16:18:52 -05002 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01007#include <assert.h>
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +01008#include <errno.h>
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +01009#include <stdbool.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010010#include <stdint.h>
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010011#include <stdio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012
13#include <platform_def.h>
14
15#include <arch_helpers.h>
16#include <common/debug.h>
17#include <lib/utils_def.h>
18#include <lib/xlat_tables/xlat_tables_defs.h>
19#include <lib/xlat_tables/xlat_tables_v2.h>
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010020
21#include "xlat_tables_private.h"
22
23#if LOG_LEVEL < LOG_LEVEL_VERBOSE
24
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010025void xlat_mmap_print(__unused const mmap_region_t *mmap)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010026{
27 /* Empty */
28}
29
30void xlat_tables_print(__unused xlat_ctx_t *ctx)
31{
32 /* Empty */
33}
34
35#else /* if LOG_LEVEL >= LOG_LEVEL_VERBOSE */
36
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010037void xlat_mmap_print(const mmap_region_t *mmap)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010038{
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010039 printf("mmap:\n");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010040 const mmap_region_t *mm = mmap;
41
42 while (mm->size != 0U) {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010043 printf(" VA:0x%lx PA:0x%llx size:0x%zx attr:0x%x granularity:0x%zx\n",
44 mm->base_va, mm->base_pa, mm->size, mm->attr,
45 mm->granularity);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010046 ++mm;
47 };
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010048 printf("\n");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010049}
50
51/* Print the attributes of the specified block descriptor. */
52static void xlat_desc_print(const xlat_ctx_t *ctx, uint64_t desc)
53{
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010054 uint64_t mem_type_index = ATTR_INDEX_GET(desc);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010055 int xlat_regime = ctx->xlat_regime;
56
57 if (mem_type_index == ATTR_IWBWA_OWBWA_NTR_INDEX) {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010058 printf("MEM");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010059 } else if (mem_type_index == ATTR_NON_CACHEABLE_INDEX) {
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010060 printf("NC");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010061 } else {
62 assert(mem_type_index == ATTR_DEVICE_INDEX);
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010063 printf("DEV");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010064 }
65
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +010066 if ((xlat_regime == EL3_REGIME) || (xlat_regime == EL2_REGIME)) {
67 /* For EL3 and EL2 only check the AP[2] and XN bits. */
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010068 printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
69 printf(((desc & UPPER_ATTRS(XN)) != 0ULL) ? "-XN" : "-EXEC");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010070 } else {
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010071 assert(xlat_regime == EL1_EL0_REGIME);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010072 /*
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010073 * For EL0 and EL1:
74 * - In AArch64 PXN and UXN can be set independently but in
75 * AArch32 there is no UXN (XN affects both privilege levels).
76 * For consistency, we set them simultaneously in both cases.
77 * - RO and RW permissions must be the same in EL1 and EL0. If
78 * EL0 can access that memory region, so can EL1, with the
79 * same permissions.
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010080 */
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010081#if ENABLE_ASSERTIONS
82 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(EL1_EL0_REGIME);
83 uint64_t xn_perm = desc & xn_mask;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010084
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010085 assert((xn_perm == xn_mask) || (xn_perm == 0ULL));
86#endif
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010087 printf(((desc & LOWER_ATTRS(AP_RO)) != 0ULL) ? "-RO" : "-RW");
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010088 /* Only check one of PXN and UXN, the other one is the same. */
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010089 printf(((desc & UPPER_ATTRS(PXN)) != 0ULL) ? "-XN" : "-EXEC");
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010090 /*
91 * Privileged regions can only be accessed from EL1, user
92 * regions can be accessed from EL1 and EL0.
93 */
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010094 printf(((desc & LOWER_ATTRS(AP_ACCESS_UNPRIVILEGED)) != 0ULL)
Antonio Nino Diaz7c1812e2018-06-27 14:59:22 +010095 ? "-USER" : "-PRIV");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +010096 }
97
Antonio Nino Diaz00086e32018-08-16 16:46:06 +010098 printf(((LOWER_ATTRS(NS) & desc) != 0ULL) ? "-NS" : "-S");
Alexei Fedorov90f2e882019-05-24 12:17:09 +010099
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700100#ifdef __aarch64__
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100101 /* Check Guarded Page bit */
102 if ((desc & GP) != 0ULL) {
103 printf("-GP");
104 }
105#endif
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100106}
107
108static const char * const level_spacers[] = {
109 "[LV0] ",
110 " [LV1] ",
111 " [LV2] ",
112 " [LV3] "
113};
114
115static const char *invalid_descriptors_ommited =
116 "%s(%d invalid descriptors omitted)\n";
117
118/*
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000119 * Recursive function that reads the translation tables passed as an argument
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100120 * and prints their status.
121 */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100122static void xlat_tables_print_internal(xlat_ctx_t *ctx, uintptr_t table_base_va,
123 const uint64_t *table_base, unsigned int table_entries,
124 unsigned int level)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100125{
126 assert(level <= XLAT_TABLE_LEVEL_MAX);
127
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000128 uint64_t desc;
David Pu36e27b82019-02-25 10:52:41 -0800129 uintptr_t table_idx_va = table_base_va;
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000130 unsigned int table_idx = 0U;
131 size_t level_size = XLAT_BLOCK_SIZE(level);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100132
133 /*
134 * Keep track of how many invalid descriptors are counted in a row.
135 * Whenever multiple invalid descriptors are found, only the first one
136 * is printed, and a line is added to inform about how many descriptors
137 * have been omitted.
138 */
139 int invalid_row_count = 0;
140
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000141 while (table_idx < table_entries) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100142
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000143 desc = table_base[table_idx];
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100144
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000145 if ((desc & DESC_MASK) == INVALID_DESC) {
146
147 if (invalid_row_count == 0) {
148 printf("%sVA:0x%lx size:0x%zx\n",
149 level_spacers[level],
150 table_idx_va, level_size);
David Pu36e27b82019-02-25 10:52:41 -0800151 }
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000152 invalid_row_count++;
153
David Pu36e27b82019-02-25 10:52:41 -0800154 } else {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100155
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000156 if (invalid_row_count > 1) {
157 printf(invalid_descriptors_ommited,
158 level_spacers[level],
159 invalid_row_count - 1);
160 }
161 invalid_row_count = 0;
162
163 /*
164 * Check if this is a table or a block. Tables are only
165 * allowed in levels other than 3, but DESC_PAGE has the
166 * same value as DESC_TABLE, so we need to check.
167 */
168 if (((desc & DESC_MASK) == TABLE_DESC) &&
169 (level < XLAT_TABLE_LEVEL_MAX)) {
David Pu36e27b82019-02-25 10:52:41 -0800170 /*
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000171 * Do not print any PA for a table descriptor,
172 * as it doesn't directly map physical memory
173 * but instead points to the next translation
174 * table in the translation table walk.
David Pu36e27b82019-02-25 10:52:41 -0800175 */
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000176 printf("%sVA:0x%lx size:0x%zx\n",
177 level_spacers[level],
178 table_idx_va, level_size);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100179
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000180 uintptr_t addr_inner = desc & TABLE_ADDR_MASK;
David Pu36e27b82019-02-25 10:52:41 -0800181
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000182 xlat_tables_print_internal(ctx, table_idx_va,
183 (uint64_t *)addr_inner,
184 XLAT_TABLE_ENTRIES, level + 1U);
185 } else {
186 printf("%sVA:0x%lx PA:0x%llx size:0x%zx ",
187 level_spacers[level], table_idx_va,
188 (uint64_t)(desc & TABLE_ADDR_MASK),
189 level_size);
190 xlat_desc_print(ctx, desc);
191 printf("\n");
David Pu36e27b82019-02-25 10:52:41 -0800192 }
193 }
Antonio Nino Diazff93d442019-03-19 14:12:09 +0000194
195 table_idx++;
196 table_idx_va += level_size;
197 }
198
199 if (invalid_row_count > 1) {
200 printf(invalid_descriptors_ommited,
201 level_spacers[level], invalid_row_count - 1);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100202 }
203}
204
205void xlat_tables_print(xlat_ctx_t *ctx)
206{
207 const char *xlat_regime_str;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100208 int used_page_tables;
209
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100210 if (ctx->xlat_regime == EL1_EL0_REGIME) {
211 xlat_regime_str = "1&0";
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100212 } else if (ctx->xlat_regime == EL2_REGIME) {
213 xlat_regime_str = "2";
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100214 } else {
215 assert(ctx->xlat_regime == EL3_REGIME);
216 xlat_regime_str = "3";
217 }
218 VERBOSE("Translation tables state:\n");
219 VERBOSE(" Xlat regime: EL%s\n", xlat_regime_str);
220 VERBOSE(" Max allowed PA: 0x%llx\n", ctx->pa_max_address);
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100221 VERBOSE(" Max allowed VA: 0x%lx\n", ctx->va_max_address);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100222 VERBOSE(" Max mapped PA: 0x%llx\n", ctx->max_pa);
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100223 VERBOSE(" Max mapped VA: 0x%lx\n", ctx->max_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100224
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100225 VERBOSE(" Initial lookup level: %u\n", ctx->base_level);
226 VERBOSE(" Entries @initial lookup level: %u\n",
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100227 ctx->base_table_entries);
228
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100229#if PLAT_XLAT_TABLES_DYNAMIC
230 used_page_tables = 0;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100231 for (int i = 0; i < ctx->tables_num; ++i) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100232 if (ctx->tables_mapped_regions[i] != 0)
233 ++used_page_tables;
234 }
235#else
236 used_page_tables = ctx->next_table;
237#endif
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100238 VERBOSE(" Used %d sub-tables out of %d (spare: %d)\n",
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100239 used_page_tables, ctx->tables_num,
240 ctx->tables_num - used_page_tables);
241
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100242 xlat_tables_print_internal(ctx, 0U, ctx->base_table,
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100243 ctx->base_table_entries, ctx->base_level);
244}
245
246#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
247
248/*
249 * Do a translation table walk to find the block or page descriptor that maps
250 * virtual_addr.
251 *
252 * On success, return the address of the descriptor within the translation
253 * table. Its lookup level is stored in '*out_level'.
254 * On error, return NULL.
255 *
256 * xlat_table_base
257 * Base address for the initial lookup level.
258 * xlat_table_base_entries
259 * Number of entries in the translation table for the initial lookup level.
260 * virt_addr_space_size
261 * Size in bytes of the virtual address space.
262 */
263static uint64_t *find_xlat_table_entry(uintptr_t virtual_addr,
264 void *xlat_table_base,
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100265 unsigned int xlat_table_base_entries,
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100266 unsigned long long virt_addr_space_size,
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100267 unsigned int *out_level)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100268{
269 unsigned int start_level;
270 uint64_t *table;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100271 unsigned int entries;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100272
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100273 start_level = GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100274
275 table = xlat_table_base;
276 entries = xlat_table_base_entries;
277
278 for (unsigned int level = start_level;
279 level <= XLAT_TABLE_LEVEL_MAX;
280 ++level) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100281 uint64_t idx, desc, desc_type;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100282
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100283 idx = XLAT_TABLE_IDX(virtual_addr, level);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100284 if (idx >= entries) {
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100285 WARN("Missing xlat table entry at address 0x%lx\n",
286 virtual_addr);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100287 return NULL;
288 }
289
290 desc = table[idx];
291 desc_type = desc & DESC_MASK;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100292
293 if (desc_type == INVALID_DESC) {
294 VERBOSE("Invalid entry (memory not mapped)\n");
295 return NULL;
296 }
297
298 if (level == XLAT_TABLE_LEVEL_MAX) {
299 /*
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100300 * Only page descriptors allowed at the final lookup
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100301 * level.
302 */
303 assert(desc_type == PAGE_DESC);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100304 *out_level = level;
305 return &table[idx];
306 }
307
308 if (desc_type == BLOCK_DESC) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100309 *out_level = level;
310 return &table[idx];
311 }
312
313 assert(desc_type == TABLE_DESC);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100314 table = (uint64_t *)(uintptr_t)(desc & TABLE_ADDR_MASK);
315 entries = XLAT_TABLE_ENTRIES;
316 }
317
318 /*
319 * This shouldn't be reached, the translation table walk should end at
320 * most at level XLAT_TABLE_LEVEL_MAX and return from inside the loop.
321 */
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +0100322 assert(false);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100323
324 return NULL;
325}
326
327
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100328static int xlat_get_mem_attributes_internal(const xlat_ctx_t *ctx,
329 uintptr_t base_va, uint32_t *attributes, uint64_t **table_entry,
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100330 unsigned long long *addr_pa, unsigned int *table_level)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100331{
332 uint64_t *entry;
333 uint64_t desc;
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100334 unsigned int level;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100335 unsigned long long virt_addr_space_size;
336
337 /*
338 * Sanity-check arguments.
339 */
340 assert(ctx != NULL);
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +0100341 assert(ctx->initialized);
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100342 assert((ctx->xlat_regime == EL1_EL0_REGIME) ||
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100343 (ctx->xlat_regime == EL2_REGIME) ||
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100344 (ctx->xlat_regime == EL3_REGIME));
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100345
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100346 virt_addr_space_size = (unsigned long long)ctx->va_max_address + 1ULL;
347 assert(virt_addr_space_size > 0U);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100348
349 entry = find_xlat_table_entry(base_va,
350 ctx->base_table,
351 ctx->base_table_entries,
352 virt_addr_space_size,
353 &level);
354 if (entry == NULL) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100355 WARN("Address 0x%lx is not mapped.\n", base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100356 return -EINVAL;
357 }
358
359 if (addr_pa != NULL) {
360 *addr_pa = *entry & TABLE_ADDR_MASK;
361 }
362
363 if (table_entry != NULL) {
364 *table_entry = entry;
365 }
366
367 if (table_level != NULL) {
368 *table_level = level;
369 }
370
371 desc = *entry;
372
373#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
374 VERBOSE("Attributes: ");
375 xlat_desc_print(ctx, desc);
Antonio Nino Diaz00086e32018-08-16 16:46:06 +0100376 printf("\n");
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100377#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
378
379 assert(attributes != NULL);
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100380 *attributes = 0U;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100381
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100382 uint64_t attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100383
384 if (attr_index == ATTR_IWBWA_OWBWA_NTR_INDEX) {
385 *attributes |= MT_MEMORY;
386 } else if (attr_index == ATTR_NON_CACHEABLE_INDEX) {
387 *attributes |= MT_NON_CACHEABLE;
388 } else {
389 assert(attr_index == ATTR_DEVICE_INDEX);
390 *attributes |= MT_DEVICE;
391 }
392
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100393 uint64_t ap2_bit = (desc >> AP2_SHIFT) & 1U;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100394
395 if (ap2_bit == AP2_RW)
396 *attributes |= MT_RW;
397
398 if (ctx->xlat_regime == EL1_EL0_REGIME) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100399 uint64_t ap1_bit = (desc >> AP1_SHIFT) & 1U;
400
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100401 if (ap1_bit == AP1_ACCESS_UNPRIVILEGED)
402 *attributes |= MT_USER;
403 }
404
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100405 uint64_t ns_bit = (desc >> NS_SHIFT) & 1U;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100406
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100407 if (ns_bit == 1U)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100408 *attributes |= MT_NS;
409
410 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(ctx->xlat_regime);
411
412 if ((desc & xn_mask) == xn_mask) {
413 *attributes |= MT_EXECUTE_NEVER;
414 } else {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100415 assert((desc & xn_mask) == 0U);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100416 }
417
418 return 0;
419}
420
421
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100422int xlat_get_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
423 uint32_t *attr)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100424{
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100425 return xlat_get_mem_attributes_internal(ctx, base_va, attr,
426 NULL, NULL, NULL);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100427}
428
429
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100430int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
431 size_t size, uint32_t attr)
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100432{
433 /* Note: This implementation isn't optimized. */
434
435 assert(ctx != NULL);
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +0100436 assert(ctx->initialized);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100437
438 unsigned long long virt_addr_space_size =
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100439 (unsigned long long)ctx->va_max_address + 1U;
440 assert(virt_addr_space_size > 0U);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100441
442 if (!IS_PAGE_ALIGNED(base_va)) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100443 WARN("%s: Address 0x%lx is not aligned on a page boundary.\n",
444 __func__, base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100445 return -EINVAL;
446 }
447
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100448 if (size == 0U) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100449 WARN("%s: Size is 0.\n", __func__);
450 return -EINVAL;
451 }
452
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100453 if ((size % PAGE_SIZE) != 0U) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100454 WARN("%s: Size 0x%zx is not a multiple of a page size.\n",
455 __func__, size);
456 return -EINVAL;
457 }
458
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100459 if (((attr & MT_EXECUTE_NEVER) == 0U) && ((attr & MT_RW) != 0U)) {
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100460 WARN("%s: Mapping memory as read-write and executable not allowed.\n",
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100461 __func__);
462 return -EINVAL;
463 }
464
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100465 size_t pages_count = size / PAGE_SIZE;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100466
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100467 VERBOSE("Changing memory attributes of %zu pages starting from address 0x%lx...\n",
468 pages_count, base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100469
470 uintptr_t base_va_original = base_va;
471
472 /*
473 * Sanity checks.
474 */
Jimmy Brissoned202072020-08-04 16:18:52 -0500475 for (unsigned int i = 0U; i < pages_count; ++i) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100476 const uint64_t *entry;
477 uint64_t desc, attr_index;
478 unsigned int level;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100479
480 entry = find_xlat_table_entry(base_va,
481 ctx->base_table,
482 ctx->base_table_entries,
483 virt_addr_space_size,
484 &level);
485 if (entry == NULL) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100486 WARN("Address 0x%lx is not mapped.\n", base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100487 return -EINVAL;
488 }
489
490 desc = *entry;
491
492 /*
493 * Check that all the required pages are mapped at page
494 * granularity.
495 */
496 if (((desc & DESC_MASK) != PAGE_DESC) ||
497 (level != XLAT_TABLE_LEVEL_MAX)) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100498 WARN("Address 0x%lx is not mapped at the right granularity.\n",
499 base_va);
Jimmy Brissoned202072020-08-04 16:18:52 -0500500 WARN("Granularity is 0x%lx, should be 0x%lx.\n",
501 XLAT_BLOCK_SIZE(level), PAGE_SIZE);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100502 return -EINVAL;
503 }
504
505 /*
506 * If the region type is device, it shouldn't be executable.
507 */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100508 attr_index = (desc >> ATTR_INDEX_SHIFT) & ATTR_INDEX_MASK;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100509 if (attr_index == ATTR_DEVICE_INDEX) {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100510 if ((attr & MT_EXECUTE_NEVER) == 0U) {
511 WARN("Setting device memory as executable at address 0x%lx.",
512 base_va);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100513 return -EINVAL;
514 }
515 }
516
517 base_va += PAGE_SIZE;
518 }
519
520 /* Restore original value. */
521 base_va = base_va_original;
522
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100523 for (unsigned int i = 0U; i < pages_count; ++i) {
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100524
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100525 uint32_t old_attr = 0U, new_attr;
526 uint64_t *entry = NULL;
527 unsigned int level = 0U;
528 unsigned long long addr_pa = 0ULL;
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100529
Antonio Nino Diaz6c4c9ee2018-08-05 15:34:10 +0100530 (void) xlat_get_mem_attributes_internal(ctx, base_va, &old_attr,
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100531 &entry, &addr_pa, &level);
532
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100533 /*
534 * From attr, only MT_RO/MT_RW, MT_EXECUTE/MT_EXECUTE_NEVER and
535 * MT_USER/MT_PRIVILEGED are taken into account. Any other
536 * information is ignored.
537 */
538
539 /* Clean the old attributes so that they can be rebuilt. */
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100540 new_attr = old_attr & ~(MT_RW | MT_EXECUTE_NEVER | MT_USER);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100541
542 /*
543 * Update attributes, but filter out the ones this function
544 * isn't allowed to change.
545 */
Antonio Nino Diazbd0aff62018-07-02 09:26:51 +0100546 new_attr |= attr & (MT_RW | MT_EXECUTE_NEVER | MT_USER);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100547
548 /*
549 * The break-before-make sequence requires writing an invalid
550 * descriptor and making sure that the system sees the change
551 * before writing the new descriptor.
552 */
553 *entry = INVALID_DESC;
Artsem Artsemenkabce728f2019-10-17 13:51:27 +0100554#if !HW_ASSISTED_COHERENCY
Antonio Nino Diaz37a5efa2018-08-07 12:47:12 +0100555 dccvac((uintptr_t)entry);
556#endif
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100557 /* Invalidate any cached copy of this mapping in the TLBs. */
Antonio Nino Diazad5dc7f2018-07-11 09:46:45 +0100558 xlat_arch_tlbi_va(base_va, ctx->xlat_regime);
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100559
560 /* Ensure completion of the invalidation. */
561 xlat_arch_tlbi_va_sync();
562
563 /* Write new descriptor */
564 *entry = xlat_desc(ctx, new_attr, addr_pa, level);
Artsem Artsemenkabce728f2019-10-17 13:51:27 +0100565#if !HW_ASSISTED_COHERENCY
Antonio Nino Diaz37a5efa2018-08-07 12:47:12 +0100566 dccvac((uintptr_t)entry);
567#endif
Antonio Nino Diazf1b84f62018-07-03 11:58:49 +0100568 base_va += PAGE_SIZE;
569 }
570
571 /* Ensure that the last descriptor writen is seen by the system. */
572 dsbish();
573
574 return 0;
575}