| developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 5 | */ |
| 6 | #ifndef __UART8250_H__ |
| 7 | #define __UART8250_H__ |
| 8 | |
| 9 | /* UART register */ |
| 10 | #define UART_RBR 0x00 /* Receive buffer register */ |
| 11 | #define UART_DLL 0x00 /* Divisor latch lsb */ |
| 12 | #define UART_THR 0x00 /* Transmit holding register */ |
| 13 | #define UART_DLH 0x04 /* Divisor latch msb */ |
| 14 | #define UART_IER 0x04 /* Interrupt enable register */ |
| 15 | #define UART_FCR 0x08 /* FIFO control register */ |
| 16 | #define UART_LCR 0x0c /* Line control register */ |
| 17 | #define UART_MCR 0x10 /* Modem control register */ |
| 18 | #define UART_LSR 0x14 /* Line status register */ |
| 19 | #define UART_HIGHSPEED 0x24 /* High speed UART */ |
| 20 | |
| 21 | /* FCR */ |
| 22 | #define UART_FCR_FIFO_EN 0x01 /* enable FIFO */ |
| 23 | #define UART_FCR_CLEAR_RCVR 0x02 /* clear the RCVR FIFO */ |
| 24 | #define UART_FCR_CLEAR_XMIT 0x04 /* clear the XMIT FIFO */ |
| 25 | |
| 26 | /* LCR */ |
| 27 | #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ |
| 28 | #define UART_LCR_DLAB 0x80 /* divisor latch access bit */ |
| 29 | |
| 30 | /* MCR */ |
| 31 | #define UART_MCR_DTR 0x01 |
| 32 | #define UART_MCR_RTS 0x02 |
| 33 | |
| 34 | /* LSR */ |
| 35 | #define UART_LSR_DR 0x01 /* Data ready */ |
| 36 | #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ |
| 37 | |
| 38 | #endif /* __UART8250_H__ */ |