Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | 4538bfc | 2019-01-02 17:53:15 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 7 | #include <arch_helpers.h> |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 8 | #include <assert.h> |
Sam Payne | 71ce6ed | 2017-05-08 12:42:49 -0700 | [diff] [blame] | 9 | #include <cortex_a57.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <common/bl_common.h> |
Varun Wadekar | 4538bfc | 2019-01-02 17:53:15 -0800 | [diff] [blame] | 11 | #include <common/debug.h> |
| 12 | #include <common/interrupt_props.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 13 | #include <drivers/console.h> |
| 14 | #include <lib/xlat_tables/xlat_tables_v2.h> |
Varun Wadekar | 4538bfc | 2019-01-02 17:53:15 -0800 | [diff] [blame] | 15 | #include <drivers/arm/gic_common.h> |
| 16 | #include <drivers/arm/gicv2.h> |
| 17 | #include <bl31/interrupt_mgmt.h> |
| 18 | |
| 19 | #include <bpmp.h> |
| 20 | #include <flowctrl.h> |
Varun Wadekar | 6e29d4d | 2018-03-07 11:13:58 -0800 | [diff] [blame] | 21 | #include <memctrl.h> |
Varun Wadekar | e34bc3d | 2017-04-28 08:43:33 -0700 | [diff] [blame] | 22 | #include <platform.h> |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 23 | #include <security_engine.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 24 | #include <tegra_def.h> |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 25 | #include <tegra_platform.h> |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 26 | #include <tegra_private.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 27 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 28 | /* sets of MMIO ranges setup */ |
| 29 | #define MMIO_RANGE_0_ADDR 0x50000000 |
| 30 | #define MMIO_RANGE_1_ADDR 0x60000000 |
| 31 | #define MMIO_RANGE_2_ADDR 0x70000000 |
| 32 | #define MMIO_RANGE_SIZE 0x200000 |
| 33 | |
| 34 | /* |
| 35 | * Table of regions to map using the MMU. |
| 36 | */ |
| 37 | static const mmap_region_t tegra_mmap[] = { |
Varun Wadekar | 08554a6 | 2017-06-12 16:47:16 -0700 | [diff] [blame] | 38 | MAP_REGION_FLAT(TEGRA_IRAM_BASE, 0x40000, /* 256KB */ |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 39 | MT_DEVICE | MT_RW | MT_SECURE), |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 40 | MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, |
| 41 | MT_DEVICE | MT_RW | MT_SECURE), |
| 42 | MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, |
| 43 | MT_DEVICE | MT_RW | MT_SECURE), |
| 44 | MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, |
| 45 | MT_DEVICE | MT_RW | MT_SECURE), |
| 46 | {0} |
| 47 | }; |
| 48 | |
| 49 | /******************************************************************************* |
| 50 | * Set up the pagetables as per the platform memory map & initialize the MMU |
| 51 | ******************************************************************************/ |
| 52 | const mmap_region_t *plat_get_mmio_map(void) |
| 53 | { |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 54 | /* Add the map region for security engine SE2 */ |
| 55 | if (tegra_chipid_is_t210_b01()) { |
| 56 | mmap_add_region((uint64_t)TEGRA_SE2_BASE, |
| 57 | (uint64_t)TEGRA_SE2_BASE, |
| 58 | (uint64_t)TEGRA_SE2_RANGE_SIZE, |
| 59 | MT_DEVICE | MT_RW | MT_SECURE); |
| 60 | } |
| 61 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 62 | /* MMIO space */ |
| 63 | return tegra_mmap; |
| 64 | } |
| 65 | |
| 66 | /******************************************************************************* |
Varun Wadekar | e34bc3d | 2017-04-28 08:43:33 -0700 | [diff] [blame] | 67 | * The Tegra power domain tree has a single system level power domain i.e. a |
| 68 | * single root node. The first entry in the power domain descriptor specifies |
| 69 | * the number of power domains at the highest power level. |
| 70 | ******************************************************************************* |
| 71 | */ |
| 72 | const unsigned char tegra_power_domain_tree_desc[] = { |
| 73 | /* No of root nodes */ |
| 74 | 1, |
| 75 | /* No of clusters */ |
| 76 | PLATFORM_CLUSTER_COUNT, |
| 77 | /* No of CPU cores - cluster0 */ |
| 78 | PLATFORM_MAX_CPUS_PER_CLUSTER, |
| 79 | /* No of CPU cores - cluster1 */ |
| 80 | PLATFORM_MAX_CPUS_PER_CLUSTER |
| 81 | }; |
| 82 | |
| 83 | /******************************************************************************* |
| 84 | * This function returns the Tegra default topology tree information. |
| 85 | ******************************************************************************/ |
| 86 | const unsigned char *plat_get_power_domain_tree_desc(void) |
| 87 | { |
| 88 | return tegra_power_domain_tree_desc; |
| 89 | } |
| 90 | |
| 91 | /******************************************************************************* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 92 | * Handler to get the System Counter Frequency |
| 93 | ******************************************************************************/ |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 94 | unsigned int plat_get_syscnt_freq2(void) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 95 | { |
| 96 | return 19200000; |
| 97 | } |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 98 | |
| 99 | /******************************************************************************* |
| 100 | * Maximum supported UART controllers |
| 101 | ******************************************************************************/ |
| 102 | #define TEGRA210_MAX_UART_PORTS 5 |
| 103 | |
| 104 | /******************************************************************************* |
| 105 | * This variable holds the UART port base addresses |
| 106 | ******************************************************************************/ |
| 107 | static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { |
| 108 | 0, /* undefined - treated as an error case */ |
| 109 | TEGRA_UARTA_BASE, |
| 110 | TEGRA_UARTB_BASE, |
| 111 | TEGRA_UARTC_BASE, |
| 112 | TEGRA_UARTD_BASE, |
| 113 | TEGRA_UARTE_BASE, |
| 114 | }; |
| 115 | |
| 116 | /******************************************************************************* |
| 117 | * Retrieve the UART controller base to be used as the console |
| 118 | ******************************************************************************/ |
| 119 | uint32_t plat_get_console_from_id(int id) |
| 120 | { |
| 121 | if (id > TEGRA210_MAX_UART_PORTS) |
| 122 | return 0; |
| 123 | |
| 124 | return tegra210_uart_addresses[id]; |
| 125 | } |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 126 | |
| 127 | /******************************************************************************* |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 128 | * Handler for early platform setup |
| 129 | ******************************************************************************/ |
| 130 | void plat_early_platform_setup(void) |
| 131 | { |
Sam Payne | 71ce6ed | 2017-05-08 12:42:49 -0700 | [diff] [blame] | 132 | const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); |
| 133 | uint64_t val; |
| 134 | |
| 135 | /* platform parameter passed by the previous bootloader */ |
| 136 | if (plat_params->l2_ecc_parity_prot_dis != 1) { |
| 137 | /* Enable ECC Parity Protection for Cortex-A57 CPUs */ |
| 138 | val = read_l2ctlr_el1(); |
| 139 | val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; |
| 140 | write_l2ctlr_el1(val); |
| 141 | } |
| 142 | |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 143 | /* Initialize security engine driver */ |
| 144 | if (tegra_chipid_is_t210_b01()) { |
| 145 | tegra_se_init(); |
| 146 | } |
| 147 | } |
| 148 | |
Varun Wadekar | 4538bfc | 2019-01-02 17:53:15 -0800 | [diff] [blame] | 149 | /* Secure IRQs for Tegra186 */ |
| 150 | static const interrupt_prop_t tegra210_interrupt_props[] = { |
| 151 | INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, GIC_HIGHEST_SEC_PRIORITY, |
| 152 | GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), |
| 153 | }; |
| 154 | |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 155 | void plat_late_platform_setup(void) |
| 156 | { |
| 157 | const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); |
Varun Wadekar | 6e29d4d | 2018-03-07 11:13:58 -0800 | [diff] [blame] | 158 | uint64_t sc7entry_end, offset; |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 159 | int ret; |
| 160 | |
| 161 | /* memmap TZDRAM area containing the SC7 Entry Firmware */ |
| 162 | if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) { |
| 163 | |
Varun Wadekar | dae2796 | 2018-03-05 10:19:37 -0800 | [diff] [blame] | 164 | assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_A_SIZE); |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 165 | |
| 166 | /* |
| 167 | * Verify that the SC7 entry firmware resides inside the TZDRAM |
Varun Wadekar | 6e29d4d | 2018-03-07 11:13:58 -0800 | [diff] [blame] | 168 | * aperture, _before_ the BL31 code and the start address is |
| 169 | * exactly 1MB from BL31 base. |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 170 | */ |
Varun Wadekar | 6e29d4d | 2018-03-07 11:13:58 -0800 | [diff] [blame] | 171 | |
| 172 | /* sc7entry-fw must be _before_ BL31 base */ |
| 173 | assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base); |
| 174 | |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 175 | sc7entry_end = plat_params->sc7entry_fw_base + |
| 176 | plat_params->sc7entry_fw_size; |
Varun Wadekar | 6e29d4d | 2018-03-07 11:13:58 -0800 | [diff] [blame] | 177 | assert(sc7entry_end < plat_params->tzdram_base); |
| 178 | |
| 179 | /* sc7entry-fw start must be exactly 1MB behind BL31 base */ |
| 180 | offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; |
| 181 | assert(offset == 0x100000); |
| 182 | |
| 183 | /* secure TZDRAM area */ |
| 184 | tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base, |
| 185 | plat_params->tzdram_size + offset); |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 186 | |
| 187 | /* power off BPMP processor until SC7 entry */ |
| 188 | tegra_fc_bpmp_off(); |
| 189 | |
| 190 | /* memmap SC7 entry firmware code */ |
| 191 | ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base, |
| 192 | plat_params->sc7entry_fw_base, |
| 193 | plat_params->sc7entry_fw_size, |
Varun Wadekar | 6e29d4d | 2018-03-07 11:13:58 -0800 | [diff] [blame] | 194 | MT_SECURE | MT_RO_DATA); |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 195 | assert(ret == 0); |
| 196 | } |
| 197 | } |
| 198 | |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 199 | /******************************************************************************* |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 200 | * Initialize the GIC and SGIs |
| 201 | ******************************************************************************/ |
| 202 | void plat_gic_setup(void) |
| 203 | { |
Varun Wadekar | 4538bfc | 2019-01-02 17:53:15 -0800 | [diff] [blame] | 204 | tegra_gic_setup(tegra210_interrupt_props, ARRAY_SIZE(tegra210_interrupt_props)); |
| 205 | |
| 206 | /* Enable handling for FIQs */ |
| 207 | tegra_fiq_handler_setup(); |
| 208 | |
| 209 | /* |
| 210 | * Enable routing watchdog FIQs from the flow controller to |
| 211 | * the GICD. |
| 212 | */ |
| 213 | tegra_fc_enable_fiq_to_ccplex_routing(); |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 214 | } |