blob: b0de0632a9fd6c2e822fb84476fee5cd5e19ebdb [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
2 * Copyright (c) 2013, ARM Limited. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32#include <string.h>
33#include <assert.h>
34#include <arch_helpers.h>
35#include <console.h>
36#include <platform.h>
37#include <psci.h>
38#include <psci_private.h>
39
40typedef int (*afflvl_on_handler)(unsigned long,
41 aff_map_node *,
42 unsigned long,
43 unsigned long);
44
45/*******************************************************************************
46 * This function checks whether a cpu which has been requested to be turned on
47 * is OFF to begin with.
48 ******************************************************************************/
49static int cpu_on_validate_state(unsigned int state)
50{
51 unsigned int psci_state;
52
53 /* Get the raw psci state */
54 psci_state = psci_get_state(state);
55
56 if (psci_state == PSCI_STATE_ON || psci_state == PSCI_STATE_SUSPEND)
57 return PSCI_E_ALREADY_ON;
58
59 if (psci_state == PSCI_STATE_ON_PENDING)
60 return PSCI_E_ON_PENDING;
61
62 assert(psci_state == PSCI_STATE_OFF);
63 return PSCI_E_SUCCESS;
64}
65
66/*******************************************************************************
67 * Handler routine to turn a cpu on. It takes care of any generic, architectural
68 * or platform specific setup required.
69 * TODO: Split this code across separate handlers for each type of setup?
70 ******************************************************************************/
71static int psci_afflvl0_on(unsigned long target_cpu,
72 aff_map_node *cpu_node,
73 unsigned long ns_entrypoint,
74 unsigned long context_id)
75{
76 unsigned int index, plat_state;
77 unsigned long psci_entrypoint;
78 int rc;
79
80 /* Sanity check to safeguard against data corruption */
81 assert(cpu_node->level == MPIDR_AFFLVL0);
82
83 /*
84 * Generic management: Ensure that the cpu is off to be
85 * turned on
86 */
87 rc = cpu_on_validate_state(cpu_node->state);
88 if (rc != PSCI_E_SUCCESS)
89 return rc;
90
91 /*
92 * Arch. management: Derive the re-entry information for
93 * the non-secure world from the non-secure state from
94 * where this call originated.
95 */
96 index = cpu_node->data;
97 rc = psci_set_ns_entry_info(index, ns_entrypoint, context_id);
98 if (rc != PSCI_E_SUCCESS)
99 return rc;
100
101 /* Set the secure world (EL3) re-entry point after BL1 */
102 psci_entrypoint = (unsigned long) psci_aff_on_finish_entry;
103
104 /*
105 * Plat. management: Give the platform the current state
106 * of the target cpu to allow it to perform the necessary
107 * steps to power on.
108 */
109 if (psci_plat_pm_ops->affinst_on) {
110
111 /* Get the current physical state of this cpu */
112 plat_state = psci_get_aff_phys_state(cpu_node);
113 rc = psci_plat_pm_ops->affinst_on(target_cpu,
114 psci_entrypoint,
115 ns_entrypoint,
116 cpu_node->level,
117 plat_state);
118 }
119
120 return rc;
121}
122
123/*******************************************************************************
124 * Handler routine to turn a cluster on. It takes care or any generic, arch.
125 * or platform specific setup required.
126 * TODO: Split this code across separate handlers for each type of setup?
127 ******************************************************************************/
128static int psci_afflvl1_on(unsigned long target_cpu,
129 aff_map_node *cluster_node,
130 unsigned long ns_entrypoint,
131 unsigned long context_id)
132{
133 int rc = PSCI_E_SUCCESS;
134 unsigned int plat_state;
135 unsigned long psci_entrypoint;
136
137 assert(cluster_node->level == MPIDR_AFFLVL1);
138
139 /*
140 * There is no generic and arch. specific cluster
141 * management required
142 */
143
144 /*
145 * Plat. management: Give the platform the current state
146 * of the target cpu to allow it to perform the necessary
147 * steps to power on.
148 */
149 if (psci_plat_pm_ops->affinst_on) {
150 plat_state = psci_get_aff_phys_state(cluster_node);
151 psci_entrypoint = (unsigned long) psci_aff_on_finish_entry;
152 rc = psci_plat_pm_ops->affinst_on(target_cpu,
153 psci_entrypoint,
154 ns_entrypoint,
155 cluster_node->level,
156 plat_state);
157 }
158
159 return rc;
160}
161
162/*******************************************************************************
163 * Handler routine to turn a cluster of clusters on. It takes care or any
164 * generic, arch. or platform specific setup required.
165 * TODO: Split this code across separate handlers for each type of setup?
166 ******************************************************************************/
167static int psci_afflvl2_on(unsigned long target_cpu,
168 aff_map_node *system_node,
169 unsigned long ns_entrypoint,
170 unsigned long context_id)
171{
172 int rc = PSCI_E_SUCCESS;
173 unsigned int plat_state;
174 unsigned long psci_entrypoint;
175
176 /* Cannot go beyond affinity level 2 in this psci imp. */
177 assert(system_node->level == MPIDR_AFFLVL2);
178
179 /*
180 * There is no generic and arch. specific system management
181 * required
182 */
183
184 /*
185 * Plat. management: Give the platform the current state
186 * of the target cpu to allow it to perform the necessary
187 * steps to power on.
188 */
189 if (psci_plat_pm_ops->affinst_on) {
190 plat_state = psci_get_aff_phys_state(system_node);
191 psci_entrypoint = (unsigned long) psci_aff_on_finish_entry;
192 rc = psci_plat_pm_ops->affinst_on(target_cpu,
193 psci_entrypoint,
194 ns_entrypoint,
195 system_node->level,
196 plat_state);
197 }
198
199 return rc;
200}
201
202/* Private data structure to make this handlers accessible through indexing */
203static const afflvl_on_handler psci_afflvl_on_handlers[] = {
204 psci_afflvl0_on,
205 psci_afflvl1_on,
206 psci_afflvl2_on,
207};
208
209/*******************************************************************************
210 * This function implements the core of the processing required to turn a cpu
211 * on. It avoids recursion to traverse from the lowest to the highest affinity
212 * level unlike the off/suspend/pon_finisher functions. It does ensure that the
213 * locks are picked in the same order as the order routines to avoid deadlocks.
214 * The flow is: Take all the locks until the highest affinity level, Call the
215 * handlers for turning an affinity level on & finally change the state of the
216 * affinity level.
217 ******************************************************************************/
218int psci_afflvl_on(unsigned long target_cpu,
219 unsigned long entrypoint,
220 unsigned long context_id,
221 int current_afflvl,
222 int target_afflvl)
223{
224 unsigned int prev_state, next_state;
225 int rc = PSCI_E_SUCCESS, level;
226 aff_map_node *aff_node;
227 unsigned long mpidr = read_mpidr() & MPIDR_AFFINITY_MASK;
228
229 /*
230 * This loop acquires the lock corresponding to each
231 * affinity level so that by the time we hit the lowest
232 * affinity level, the system topology is snapshot and
233 * state management can be done safely.
234 */
235 for (level = current_afflvl; level >= target_afflvl; level--) {
236 aff_node = psci_get_aff_map_node(target_cpu, level);
237 if (aff_node)
238 bakery_lock_get(mpidr, &aff_node->lock);
239 }
240
241 /*
242 * Perform generic, architecture and platform specific
243 * handling
244 */
245 for (level = current_afflvl; level >= target_afflvl; level--) {
246
247 /* Grab the node for each affinity level once again */
248 aff_node = psci_get_aff_map_node(target_cpu, level);
249 if (aff_node) {
250
251 /* Keep the old state and the next one handy */
252 prev_state = psci_get_state(aff_node->state);
253 rc = psci_afflvl_on_handlers[level](target_cpu,
254 aff_node,
255 entrypoint,
256 context_id);
257 if (rc != PSCI_E_SUCCESS) {
258 psci_set_state(aff_node->state, prev_state);
259 goto exit;
260 }
261 }
262 }
263
264 /*
265 * State management: Update the states since this is the
266 * target affinity level requested.
267 */
268 psci_change_state(target_cpu,
269 target_afflvl,
270 get_max_afflvl(),
271 PSCI_STATE_ON_PENDING);
272
273exit:
274 /*
275 * This loop releases the lock corresponding to each affinity level
276 * in the reverse order. It also checks the final state of the cpu.
277 */
278 for (level = target_afflvl; level <= current_afflvl; level++) {
279 aff_node = psci_get_aff_map_node(target_cpu, level);
280 if (aff_node) {
281 if (level == MPIDR_AFFLVL0) {
282 next_state = psci_get_state(aff_node->state);
283 assert(next_state == PSCI_STATE_ON_PENDING);
284 }
285 bakery_lock_release(mpidr, &aff_node->lock);
286 }
287 }
288
289 return rc;
290}
291
292/*******************************************************************************
293 * The following functions finish an earlier affinity power on request. They
294 * are called by the common finisher routine in psci_common.c.
295 ******************************************************************************/
296static unsigned int psci_afflvl0_on_finish(unsigned long mpidr,
297 aff_map_node *cpu_node,
298 unsigned int prev_state)
299{
300 unsigned int index, plat_state, rc = PSCI_E_SUCCESS;
301
302 assert(cpu_node->level == MPIDR_AFFLVL0);
303
304 /*
305 * Plat. management: Perform the platform specific actions
306 * for this cpu e.g. enabling the gic or zeroing the mailbox
307 * register. The actual state of this cpu has already been
308 * changed.
309 */
310 if (psci_plat_pm_ops->affinst_on_finish) {
311
312 /* Get the previous physical state of this cpu */
313 plat_state = psci_get_phys_state(prev_state);
314 rc = psci_plat_pm_ops->affinst_on_finish(mpidr,
315 cpu_node->level,
316 plat_state);
317 assert(rc == PSCI_E_SUCCESS);
318 }
319
320 /*
321 * Arch. management: Turn on mmu & restore architectural state
322 */
323 write_vbar((unsigned long) runtime_exceptions);
324 enable_mmu();
325
326 /*
327 * All the platform specific actions for turning this cpu
328 * on have completed. Perform enough arch.initialization
329 * to run in the non-secure address space.
330 */
331 bl31_arch_setup();
332
333 /*
334 * Generic management: Now we just need to retrieve the
335 * information that we had stashed away during the cpu_on
336 * call to set this cpu on it's way. First get the index
337 * for restoring the re-entry info
338 */
339 index = cpu_node->data;
340 rc = psci_get_ns_entry_info(index);
341
342 /* Clean caches before re-entering normal world */
343 dcsw_op_louis(DCCSW);
344
345 return rc;
346}
347
348static unsigned int psci_afflvl1_on_finish(unsigned long mpidr,
349 aff_map_node *cluster_node,
350 unsigned int prev_state)
351{
352 unsigned int rc = PSCI_E_SUCCESS;
353 unsigned int plat_state;
354
355 assert(cluster_node->level == MPIDR_AFFLVL1);
356
357 /*
358 * Plat. management: Perform the platform specific actions
359 * as per the old state of the cluster e.g. enabling
360 * coherency at the interconnect depends upon the state with
361 * which this cluster was powered up. If anything goes wrong
362 * then assert as there is no way to recover from this
363 * situation.
364 */
365 if (psci_plat_pm_ops->affinst_on_finish) {
366 plat_state = psci_get_phys_state(prev_state);
367 rc = psci_plat_pm_ops->affinst_on_finish(mpidr,
368 cluster_node->level,
369 plat_state);
370 assert(rc == PSCI_E_SUCCESS);
371 }
372
373 return rc;
374}
375
376
377static unsigned int psci_afflvl2_on_finish(unsigned long mpidr,
378 aff_map_node *system_node,
379 unsigned int prev_state)
380{
381 int rc = PSCI_E_SUCCESS;
382 unsigned int plat_state;
383
384 /* Cannot go beyond this affinity level */
385 assert(system_node->level == MPIDR_AFFLVL2);
386
387 /*
388 * Currently, there are no architectural actions to perform
389 * at the system level.
390 */
391
392 /*
393 * Plat. management: Perform the platform specific actions
394 * as per the old state of the cluster e.g. enabling
395 * coherency at the interconnect depends upon the state with
396 * which this cluster was powered up. If anything goes wrong
397 * then assert as there is no way to recover from this
398 * situation.
399 */
400 if (psci_plat_pm_ops->affinst_on_finish) {
401 plat_state = psci_get_phys_state(system_node->state);
402 rc = psci_plat_pm_ops->affinst_on_finish(mpidr,
403 system_node->level,
404 plat_state);
405 assert(rc == PSCI_E_SUCCESS);
406 }
407
408 return rc;
409}
410
411const afflvl_power_on_finisher psci_afflvl_on_finishers[] = {
412 psci_afflvl0_on_finish,
413 psci_afflvl1_on_finish,
414 psci_afflvl2_on_finish,
415};
416