blob: 492c45bb599a7e8d210240786172936c1f7c0ef8 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
32#include <platform.h>
33#include <assert.h>
34
35/*******************************************************************************
36 * This duplicates what the primary cpu did after a cold boot in BL1. The same
37 * needs to be done when a cpu is hotplugged in. This function could also over-
38 * ride any EL3 setup done by BL1 as this code resides in rw memory.
39 ******************************************************************************/
40void bl31_arch_setup(void)
41{
42 unsigned long tmp_reg = 0;
43 unsigned int counter_base_frequency;
44
45 /* Enable alignment checks and set the exception endianness to LE */
46 tmp_reg = read_sctlr();
47 tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT);
48 tmp_reg &= ~SCTLR_EE_BIT;
49 write_sctlr(tmp_reg);
50
51 /*
Sandrine Bailleux37382742013-11-18 17:26:59 +000052 * Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route
53 * external abort and SError interrupts to EL3
Achin Gupta4f6ad662013-10-25 09:08:21 +010054 */
Sandrine Bailleux37382742013-11-18 17:26:59 +000055 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_EA_BIT |
56 SCR_FIQ_BIT;
Achin Gupta4f6ad662013-10-25 09:08:21 +010057 write_scr(tmp_reg);
58
Sandrine Bailleux37382742013-11-18 17:26:59 +000059 /*
60 * Enable SError and Debug exceptions
61 */
62 enable_serror();
63 enable_debug_exceptions();
64
Achin Gupta4f6ad662013-10-25 09:08:21 +010065 /* Read the frequency from Frequency modes table */
66 counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
67 /* The first entry of the frequency modes table must not be 0 */
68 assert(counter_base_frequency != 0);
69
70 /* Program the counter frequency */
71 write_cntfrq_el0(counter_base_frequency);
72 return;
73}
74
75/*******************************************************************************
76 * Detect what is the next Non-Secure EL and setup the required architectural
77 * state
78 ******************************************************************************/
79void bl31_arch_next_el_setup(void) {
80 unsigned long id_aa64pfr0 = read_id_aa64pfr0_el1();
81 unsigned long current_sctlr, next_sctlr;
82 unsigned long el_status;
83 unsigned long scr = read_scr();
84
85 /* Use the same endianness than the current BL */
86 current_sctlr = read_sctlr();
87 next_sctlr = (current_sctlr & SCTLR_EE_BIT);
88
89 /* Find out which EL we are going to */
90 el_status = (id_aa64pfr0 >> ID_AA64PFR0_EL2_SHIFT) & ID_AA64PFR0_ELX_MASK;
91
92 /* Check what if EL2 is supported */
93 if (el_status && (scr & SCR_HCE_BIT)) {
94 /* Set SCTLR EL2 */
95 next_sctlr |= SCTLR_EL2_RES1;
96
97 write_sctlr_el2(next_sctlr);
98 } else {
99 /* Set SCTLR Non-Secure EL1 */
100 next_sctlr |= SCTLR_EL1_RES1;
101
102 write_sctlr_el1(next_sctlr);
103 }
104}