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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -07002 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 */
6
7#include <assert.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -08008#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <bl31/bl31.h>
11#include <common/bl_common.h>
12#include <common/debug.h>
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -070013#include <drivers/arm/dcc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <drivers/console.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000015#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <plat/common/platform.h>
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -070017#include <lib/mmio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -070019#include <plat_startup.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000020#include <plat_private.h>
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -070021#include <zynqmp_def.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000022
Michal Simek53865b02021-05-27 09:42:37 +020023#include <common/fdt_fixup.h>
24#include <common/fdt_wrappers.h>
25#include <libfdt.h>
26
Soren Brinkmann76fcae32016-03-06 20:16:27 -080027static entry_point_info_t bl32_image_ep_info;
28static entry_point_info_t bl33_image_ep_info;
29
30/*
31 * Return a pointer to the 'entry_point_info' structure of the next image for
32 * the security state specified. BL33 corresponds to the non-secure image type
33 * while BL32 corresponds to the secure image type. A NULL pointer is returned
34 * if the image does not exist.
35 */
36entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
37{
38 assert(sec_state_is_valid(type));
39
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -070040 if (type == NON_SECURE) {
Soren Brinkmann76fcae32016-03-06 20:16:27 -080041 return &bl33_image_ep_info;
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -070042 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -080043
44 return &bl32_image_ep_info;
45}
46
47/*
Alistair Francisb8d474f2017-11-30 16:21:21 -080048 * Set the build time defaults. We want to do this when doing a JTAG boot
49 * or if we can't find any other config data.
50 */
51static inline void bl31_set_default_config(void)
52{
53 bl32_image_ep_info.pc = BL32_BASE;
54 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
55 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
56 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
57 DISABLE_ALL_EXCEPTIONS);
58}
59
60/*
Soren Brinkmann76fcae32016-03-06 20:16:27 -080061 * Perform any BL31 specific platform actions. Here is an opportunity to copy
John Tsichritzisd653d332018-09-14 10:34:57 +010062 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
Soren Brinkmann76fcae32016-03-06 20:16:27 -080063 * are lost (potentially). This needs to be done before the MMU is initialized
64 * so that the memory layout can be used while creating page tables.
65 */
Antonio Nino Diaz012c8bf2018-09-24 17:16:52 +010066void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
67 u_register_t arg2, u_register_t arg3)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080068{
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -070069 uint64_t atf_handoff_addr;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080070
Venkatesh Yadav Abbarapu0bd80de2021-12-19 21:32:00 -070071 if (ZYNQMP_CONSOLE_IS(cadence) || (ZYNQMP_CONSOLE_IS(cadence1))) {
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -070072 /* Register the console to provide early debug support */
73 static console_t bl31_boot_console;
74 (void)console_cdns_register(ZYNQMP_UART_BASE,
75 zynqmp_get_uart_clk(),
76 ZYNQMP_UART_BAUDRATE,
77 &bl31_boot_console);
78 console_set_scope(&bl31_boot_console,
79 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
80 } else if (ZYNQMP_CONSOLE_IS(dcc)) {
81 /* Initialize the dcc console for debug */
82 int rc = console_dcc_register();
83 if (rc == 0) {
84 panic();
85 }
86 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -080087 /* Initialize the platform config for future decision making */
88 zynqmp_config_setup();
89
90 /* There are no parameters from BL2 if BL31 is a reset vector */
Antonio Nino Diaz012c8bf2018-09-24 17:16:52 +010091 assert(arg0 == 0U);
92 assert(arg1 == 0U);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080093
94 /*
95 * Do initial security configuration to allow DRAM/device access. On
96 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but
97 * other platforms might have more programmable security devices
98 * present.
99 */
100
Michal Simekef8f5592015-06-15 14:22:50 +0200101 /* Populate common information for BL32 and BL33 */
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800102 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
103 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800104 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800105 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
106
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -0700107 atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6);
108
Michal Simekef8f5592015-06-15 14:22:50 +0200109 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
Alistair Francisb8d474f2017-11-30 16:21:21 -0800110 bl31_set_default_config();
Michal Simekef8f5592015-06-15 14:22:50 +0200111 } else {
112 /* use parameters from FSBL */
Siva Durga Prasad Paladugu8f499722018-05-17 15:17:46 +0530113 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -0700114 &bl33_image_ep_info,
115 atf_handoff_addr);
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700116 if (ret == FSBL_HANDOFF_NO_STRUCT) {
Alistair Francisb8d474f2017-11-30 16:21:21 -0800117 bl31_set_default_config();
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700118 } else if (ret != FSBL_HANDOFF_SUCCESS) {
Siva Durga Prasad Paladugu8f499722018-05-17 15:17:46 +0530119 panic();
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700120 }
Michal Simekef8f5592015-06-15 14:22:50 +0200121 }
Venkatesh Yadav Abbarapu621c1b22020-01-10 03:01:35 -0700122 if (bl32_image_ep_info.pc) {
123 VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
124 }
125 if (bl33_image_ep_info.pc) {
126 VERBOSE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
127 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800128}
129
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530130#if ZYNQMP_WDT_RESTART
131static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3];
132
133int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
134{
135 /* Validate 'handler' and 'id' parameters */
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700136 if (!handler || id >= MAX_INTR_EL3) {
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530137 return -EINVAL;
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700138 }
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530139
140 /* Check if a handler has already been registered */
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700141 if (type_el3_interrupt_table[id]) {
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530142 return -EALREADY;
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700143 }
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530144
145 type_el3_interrupt_table[id] = handler;
146
147 return 0;
148}
149
150static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
151 void *handle, void *cookie)
152{
153 uint32_t intr_id;
154 interrupt_type_handler_t handler;
155
156 intr_id = plat_ic_get_pending_interrupt_id();
157 handler = type_el3_interrupt_table[intr_id];
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700158 if (handler != NULL) {
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530159 handler(intr_id, flags, handle, cookie);
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700160 }
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530161
162 return 0;
163}
164#endif
165
Michal Simek53865b02021-05-27 09:42:37 +0200166#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
167static void prepare_dtb(void)
168{
169 void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
170 int ret;
171
172 /* Return if no device tree is detected */
173 if (fdt_check_header(dtb) != 0) {
174 NOTICE("Can't read DT at 0x%p\n", dtb);
175 return;
176 }
177
178 ret = fdt_open_into(dtb, dtb, XILINX_OF_BOARD_DTB_MAX_SIZE);
179 if (ret < 0) {
180 ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret);
181 return;
182 }
183
184 if (dt_add_psci_node(dtb)) {
185 ERROR("Failed to add PSCI Device Tree node\n");
186 return;
187 }
188
189 if (dt_add_psci_cpu_enable_methods(dtb)) {
190 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
191 return;
192 }
193
194 /* Reserve memory used by Trusted Firmware. */
195 if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, BL31_LIMIT - BL31_BASE)) {
196 WARN("Failed to add reserved memory nodes to DT.\n");
197 }
198
199 ret = fdt_pack(dtb);
200 if (ret < 0) {
201 ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret);
202 }
203
204 clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
205 INFO("Changed device tree to advertise PSCI and reserved memories.\n");
206}
207#endif
208
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800209void bl31_platform_setup(void)
210{
Michal Simek53865b02021-05-27 09:42:37 +0200211#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
212 prepare_dtb();
213#endif
214
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800215 /* Initialize the gic cpu and distributor interfaces */
216 plat_arm_gic_driver_init();
217 plat_arm_gic_init();
218}
219
220void bl31_plat_runtime_setup(void)
221{
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530222#if ZYNQMP_WDT_RESTART
223 uint64_t flags = 0;
224 uint64_t rc;
225
226 set_interrupt_rm_flag(flags, NON_SECURE);
227 rc = register_interrupt_type_handler(INTR_TYPE_EL3,
228 rdo_el3_interrupt_handler, flags);
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700229 if (rc) {
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530230 panic();
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700231 }
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530232#endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800233}
234
235/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100236 * Perform the very early platform specific architectural setup here.
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800237 */
238void bl31_plat_arch_setup(void)
239{
240 plat_arm_interconnect_init();
241 plat_arm_interconnect_enter_coherency();
242
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100243
244 const mmap_region_t bl_regions[] = {
Michal Simek53865b02021-05-27 09:42:37 +0200245#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
246 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
247 MT_MEMORY | MT_RW | MT_NS),
248#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100249 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
250 MT_MEMORY | MT_RW | MT_SECURE),
251 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
252 MT_CODE | MT_SECURE),
253 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
254 MT_RO_DATA | MT_SECURE),
255 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
256 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
257 MT_DEVICE | MT_RW | MT_SECURE),
258 {0}
259 };
260
Roberto Vargas344ff022018-10-19 16:44:18 +0100261 setup_page_tables(bl_regions, plat_arm_get_mmap());
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100262 enable_mmu_el3(0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800263}