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Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00001/*
Carlo Caione1afdfb02019-08-24 18:47:06 +01002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
Carlo Caione41f0ed32019-09-03 12:38:58 +01008#include <bl31/interrupt_mgmt.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00009#include <common/bl_common.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000010#include <common/ep_info.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000011#include <lib/mmio.h>
Carlo Caione41f0ed32019-09-03 12:38:58 +010012#include <lib/xlat_tables/xlat_tables_v2.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000013#include <platform_def.h>
14#include <stdint.h>
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000015
16/*******************************************************************************
17 * Platform memory map regions
18 ******************************************************************************/
Carlo Caione1e3e33b2019-08-28 15:32:22 +010019#define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
20 AML_NSDRAM0_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000021 MT_MEMORY | MT_RW | MT_NS)
22
Carlo Caione1e3e33b2019-08-28 15:32:22 +010023#define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
24 AML_NSDRAM1_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000025 MT_MEMORY | MT_RW | MT_NS)
26
Carlo Caione1e3e33b2019-08-28 15:32:22 +010027#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
28 AML_SEC_DEVICE0_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000029 MT_DEVICE | MT_RW | MT_SECURE)
30
Carlo Caione1e3e33b2019-08-28 15:32:22 +010031#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
32 AML_SEC_DEVICE1_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000033 MT_DEVICE | MT_RW | MT_SECURE)
34
Carlo Caione41f0ed32019-09-03 12:38:58 +010035#define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
36 AML_TZRAM_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000037 MT_DEVICE | MT_RW | MT_SECURE)
38
Carlo Caione1e3e33b2019-08-28 15:32:22 +010039#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
40 AML_SEC_DEVICE2_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000041 MT_DEVICE | MT_RW | MT_SECURE)
42
Carlo Caione1e3e33b2019-08-28 15:32:22 +010043#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
44 AML_SEC_DEVICE3_SIZE, \
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000045 MT_DEVICE | MT_RW | MT_SECURE)
46
Carlo Caione1e3e33b2019-08-28 15:32:22 +010047static const mmap_region_t gxl_mmap[] = {
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000048 MAP_NSDRAM0,
49 MAP_NSDRAM1,
50 MAP_SEC_DEVICE0,
51 MAP_SEC_DEVICE1,
52 MAP_TZRAM,
53 MAP_SEC_DEVICE2,
54 MAP_SEC_DEVICE3,
55 {0}
56};
57
58/*******************************************************************************
59 * Per-image regions
60 ******************************************************************************/
61#define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
62 BL31_END - BL31_BASE, \
63 MT_MEMORY | MT_RW | MT_SECURE)
64
65#define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
66 BL_CODE_END - BL_CODE_BASE, \
67 MT_CODE | MT_SECURE)
68
69#define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
70 BL_RO_DATA_END - BL_RO_DATA_BASE, \
71 MT_RO_DATA | MT_SECURE)
72
73#define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \
74 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
75 MT_DEVICE | MT_RW | MT_SECURE)
76
77/*******************************************************************************
78 * Function that sets up the translation tables.
79 ******************************************************************************/
Carlo Caionebf2d6262019-08-25 18:09:03 +010080void aml_setup_page_tables(void)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000081{
82#if IMAGE_BL31
Carlo Caione1e3e33b2019-08-28 15:32:22 +010083 const mmap_region_t gxl_bl_mmap[] = {
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000084 MAP_BL31,
85 MAP_BL_CODE,
86 MAP_BL_RO_DATA,
87#if USE_COHERENT_MEM
88 MAP_BL_COHERENT,
89#endif
90 {0}
91 };
92#endif
93
Carlo Caione1e3e33b2019-08-28 15:32:22 +010094 mmap_add(gxl_bl_mmap);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000095
Carlo Caione1e3e33b2019-08-28 15:32:22 +010096 mmap_add(gxl_mmap);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000097
98 init_xlat_tables();
99}
100
101/*******************************************************************************
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000102 * Function that returns the system counter frequency
103 ******************************************************************************/
104unsigned int plat_get_syscnt_freq2(void)
105{
106 uint32_t val;
107
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100108 val = mmio_read_32(AML_SYS_CPU_CFG7);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000109 val &= 0xFDFFFFFF;
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100110 mmio_write_32(AML_SYS_CPU_CFG7, val);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000111
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100112 val = mmio_read_32(AML_AO_TIMESTAMP_CNTL);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000113 val &= 0xFFFFFE00;
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100114 mmio_write_32(AML_AO_TIMESTAMP_CNTL, val);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000115
Carlo Caione1e3e33b2019-08-28 15:32:22 +0100116 return AML_OSC24M_CLK_IN_HZ;
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000117}