blob: d9144d87577cf56dfa150630113ab5789e888f2e [file] [log] [blame]
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +08001/*
jason-ch chena07e3ea2021-11-16 10:18:46 +08002 * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/debug.h>
8#include <common/runtime_svc.h>
jason-ch chena07e3ea2021-11-16 10:18:46 +08009#include <mt_spm_vcorefs.h>
10#include <mtk_sip_svc.h>
Rex-BC Chen1782ce92021-12-02 14:03:44 +080011#include <plat_dfd.h>
jason-ch chena07e3ea2021-11-16 10:18:46 +080012#include "plat_sip_calls.h"
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +080013
14uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
15 u_register_t x1,
16 u_register_t x2,
17 u_register_t x3,
18 u_register_t x4,
19 void *cookie,
20 void *handle,
21 u_register_t flags)
22{
jason-ch chena07e3ea2021-11-16 10:18:46 +080023 uint64_t ret;
24
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +080025 switch (smc_fid) {
developer8c327e82022-05-29 22:25:44 +080026 case MTK_SIP_VCORE_CONTROL_AARCH32:
27 case MTK_SIP_VCORE_CONTROL_AARCH64:
jason-ch chena07e3ea2021-11-16 10:18:46 +080028 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
29 SMC_RET2(handle, ret, x4);
30 break;
Rex-BC Chen1782ce92021-12-02 14:03:44 +080031 case MTK_SIP_KERNEL_DFD_AARCH32:
32 case MTK_SIP_KERNEL_DFD_AARCH64:
33 ret = dfd_smc_dispatcher(x1, x2, x3, x4);
34 SMC_RET1(handle, ret);
35 break;
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +080036 default:
37 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
38 break;
39 }
40
41 SMC_RET1(handle, SMC_UNK);
42}