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git01.mediatek.com / filogic / atf / 4ee7b674a1561934242dcc777896eb4fc2583a17 / . / drivers / staging / renesas / rcar / pfc / H3 / pfc_init_h3_v1.c
blob: 632981b06b2e96d3c243b2022e67c37c1f8c79a6 [file] [log] [blame]
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1/*
Marek Vasut4ee7b672019-06-17 18:49:35 +0200[diff] [blame^]2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]7#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]8#include <lib/mmio.h>
Marek Vasut4ee7b672019-06-17 18:49:35 +0200[diff] [blame^]9#include "../pfc_regs.h"
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]10
11#define GPSR0_D15 ((uint32_t)1U << 15U)
12#define GPSR0_D14 ((uint32_t)1U << 14U)
13#define GPSR0_D13 ((uint32_t)1U << 13U)
14#define GPSR0_D12 ((uint32_t)1U << 12U)
15#define GPSR0_D11 ((uint32_t)1U << 11U)
16#define GPSR0_D10 ((uint32_t)1U << 10U)
17#define GPSR0_D9 ((uint32_t)1U << 9U)
18#define GPSR0_D8 ((uint32_t)1U << 8U)
19#define GPSR0_D7 ((uint32_t)1U << 7U)
20#define GPSR0_D6 ((uint32_t)1U << 6U)
21#define GPSR0_D5 ((uint32_t)1U << 5U)
22#define GPSR0_D4 ((uint32_t)1U << 4U)
23#define GPSR0_D3 ((uint32_t)1U << 3U)
24#define GPSR0_D2 ((uint32_t)1U << 2U)
25#define GPSR0_D1 ((uint32_t)1U << 1U)
26#define GPSR0_D0 ((uint32_t)1U << 0U)
27#define GPSR1_EX_WAIT0_A ((uint32_t)1U << 27U)
28#define GPSR1_WE1 ((uint32_t)1U << 26U)
29#define GPSR1_WE0 ((uint32_t)1U << 25U)
30#define GPSR1_RD_WR ((uint32_t)1U << 24U)
31#define GPSR1_RD ((uint32_t)1U << 23U)
32#define GPSR1_BS ((uint32_t)1U << 22U)
33#define GPSR1_CS1_A26 ((uint32_t)1U << 21U)
34#define GPSR1_CS0 ((uint32_t)1U << 20U)
35#define GPSR1_A19 ((uint32_t)1U << 19U)
36#define GPSR1_A18 ((uint32_t)1U << 18U)
37#define GPSR1_A17 ((uint32_t)1U << 17U)
38#define GPSR1_A16 ((uint32_t)1U << 16U)
39#define GPSR1_A15 ((uint32_t)1U << 15U)
40#define GPSR1_A14 ((uint32_t)1U << 14U)
41#define GPSR1_A13 ((uint32_t)1U << 13U)
42#define GPSR1_A12 ((uint32_t)1U << 12U)
43#define GPSR1_A11 ((uint32_t)1U << 11U)
44#define GPSR1_A10 ((uint32_t)1U << 10U)
45#define GPSR1_A9 ((uint32_t)1U << 9U)
46#define GPSR1_A8 ((uint32_t)1U << 8U)
47#define GPSR1_A7 ((uint32_t)1U << 7U)
48#define GPSR1_A6 ((uint32_t)1U << 6U)
49#define GPSR1_A5 ((uint32_t)1U << 5U)
50#define GPSR1_A4 ((uint32_t)1U << 4U)
51#define GPSR1_A3 ((uint32_t)1U << 3U)
52#define GPSR1_A2 ((uint32_t)1U << 2U)
53#define GPSR1_A1 ((uint32_t)1U << 1U)
54#define GPSR1_A0 ((uint32_t)1U << 0U)
55#define GPSR2_AVB_AVTP_CAPTURE_A ((uint32_t)1U << 14U)
56#define GPSR2_AVB_AVTP_MATCH_A ((uint32_t)1U << 13U)
57#define GPSR2_AVB_LINK ((uint32_t)1U << 12U)
58#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 11U)
59#define GPSR2_AVB_MAGIC ((uint32_t)1U << 10U)
60#define GPSR2_AVB_MDC ((uint32_t)1U << 9U)
61#define GPSR2_PWM2_A ((uint32_t)1U << 8U)
62#define GPSR2_PWM1_A ((uint32_t)1U << 7U)
63#define GPSR2_PWM0 ((uint32_t)1U << 6U)
64#define GPSR2_IRQ5 ((uint32_t)1U << 5U)
65#define GPSR2_IRQ4 ((uint32_t)1U << 4U)
66#define GPSR2_IRQ3 ((uint32_t)1U << 3U)
67#define GPSR2_IRQ2 ((uint32_t)1U << 2U)
68#define GPSR2_IRQ1 ((uint32_t)1U << 1U)
69#define GPSR2_IRQ0 ((uint32_t)1U << 0U)
70#define GPSR3_SD1_WP ((uint32_t)1U << 15U)
71#define GPSR3_SD1_CD ((uint32_t)1U << 14U)
72#define GPSR3_SD0_WP ((uint32_t)1U << 13U)
73#define GPSR3_SD0_CD ((uint32_t)1U << 12U)
74#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U)
75#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U)
76#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U)
77#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U)
78#define GPSR3_SD1_CMD ((uint32_t)1U << 7U)
79#define GPSR3_SD1_CLK ((uint32_t)1U << 6U)
80#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U)
81#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U)
82#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U)
83#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U)
84#define GPSR3_SD0_CMD ((uint32_t)1U << 1U)
85#define GPSR3_SD0_CLK ((uint32_t)1U << 0U)
86#define GPSR4_SD3_DS ((uint32_t)1U << 17U)
87#define GPSR4_SD3_DAT7 ((uint32_t)1U << 16U)
88#define GPSR4_SD3_DAT6 ((uint32_t)1U << 15U)
89#define GPSR4_SD3_DAT5 ((uint32_t)1U << 14U)
90#define GPSR4_SD3_DAT4 ((uint32_t)1U << 13U)
91#define GPSR4_SD3_DAT3 ((uint32_t)1U << 12U)
92#define GPSR4_SD3_DAT2 ((uint32_t)1U << 11U)
93#define GPSR4_SD3_DAT1 ((uint32_t)1U << 10U)
94#define GPSR4_SD3_DAT0 ((uint32_t)1U << 9U)
95#define GPSR4_SD3_CMD ((uint32_t)1U << 8U)
96#define GPSR4_SD3_CLK ((uint32_t)1U << 7U)
97#define GPSR4_SD2_DS ((uint32_t)1U << 6U)
98#define GPSR4_SD2_DAT3 ((uint32_t)1U << 5U)
99#define GPSR4_SD2_DAT2 ((uint32_t)1U << 4U)
100#define GPSR4_SD2_DAT1 ((uint32_t)1U << 3U)
101#define GPSR4_SD2_DAT0 ((uint32_t)1U << 2U)
102#define GPSR4_SD2_CMD ((uint32_t)1U << 1U)
103#define GPSR4_SD2_CLK ((uint32_t)1U << 0U)
104#define GPSR5_MLB_DAT ((uint32_t)1U << 25U)
105#define GPSR5_MLB_SIG ((uint32_t)1U << 24U)
106#define GPSR5_MLB_CLK ((uint32_t)1U << 23U)
107#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 22U)
108#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 21U)
109#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 20U)
110#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 19U)
111#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 18U)
112#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 17U)
113#define GPSR5_HRTS0 ((uint32_t)1U << 16U)
114#define GPSR5_HCTS0 ((uint32_t)1U << 15U)
115#define GPSR5_HTX0 ((uint32_t)1U << 14U)
116#define GPSR5_HRX0 ((uint32_t)1U << 13U)
117#define GPSR5_HSCK0 ((uint32_t)1U << 12U)
118#define GPSR5_RX2_A ((uint32_t)1U << 11U)
119#define GPSR5_TX2_A ((uint32_t)1U << 10U)
120#define GPSR5_SCK2 ((uint32_t)1U << 9U)
121#define GPSR5_RTS1_TANS ((uint32_t)1U << 8U)
122#define GPSR5_CTS1 ((uint32_t)1U << 7U)
123#define GPSR5_TX1_A ((uint32_t)1U << 6U)
124#define GPSR5_RX1_A ((uint32_t)1U << 5U)
125#define GPSR5_RTS0_TANS ((uint32_t)1U << 4U)
126#define GPSR5_CTS0 ((uint32_t)1U << 3U)
127#define GPSR5_TX0 ((uint32_t)1U << 2U)
128#define GPSR5_RX0 ((uint32_t)1U << 1U)
129#define GPSR5_SCK0 ((uint32_t)1U << 0U)
130#define GPSR6_USB31_OVC ((uint32_t)1U << 31U)
131#define GPSR6_USB31_PWEN ((uint32_t)1U << 30U)
132#define GPSR6_USB30_OVC ((uint32_t)1U << 29U)
133#define GPSR6_USB30_PWEN ((uint32_t)1U << 28U)
134#define GPSR6_USB1_OVC ((uint32_t)1U << 27U)
135#define GPSR6_USB1_PWEN ((uint32_t)1U << 26U)
136#define GPSR6_USB0_OVC ((uint32_t)1U << 25U)
137#define GPSR6_USB0_PWEN ((uint32_t)1U << 24U)
138#define GPSR6_AUDIO_CLKB_B ((uint32_t)1U << 23U)
139#define GPSR6_AUDIO_CLKA_A ((uint32_t)1U << 22U)
140#define GPSR6_SSI_SDATA9_A ((uint32_t)1U << 21U)
141#define GPSR6_SSI_SDATA8 ((uint32_t)1U << 20U)
142#define GPSR6_SSI_SDATA7 ((uint32_t)1U << 19U)
143#define GPSR6_SSI_WS78 ((uint32_t)1U << 18U)
144#define GPSR6_SSI_SCK78 ((uint32_t)1U << 17U)
145#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U)
146#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U)
147#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U)
148#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U)
149#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U)
150#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U)
151#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U)
152#define GPSR6_SSI_WS4 ((uint32_t)1U << 9U)
153#define GPSR6_SSI_SCK4 ((uint32_t)1U << 8U)
154#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U)
155#define GPSR6_SSI_WS34 ((uint32_t)1U << 6U)
156#define GPSR6_SSI_SCK34 ((uint32_t)1U << 5U)
157#define GPSR6_SSI_SDATA2_A ((uint32_t)1U << 4U)
158#define GPSR6_SSI_SDATA1_A ((uint32_t)1U << 3U)
159#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U)
160#define GPSR6_SSI_WS0129 ((uint32_t)1U << 1U)
161#define GPSR6_SSI_SCK0129 ((uint32_t)1U << 0U)
162#define GPSR7_HDMI1_CEC ((uint32_t)1U << 3U)
163#define GPSR7_HDMI0_CEC ((uint32_t)1U << 2U)
164#define GPSR7_AVS2 ((uint32_t)1U << 1U)
165#define GPSR7_AVS1 ((uint32_t)1U << 0U)
166
167#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
168#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
169#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
170#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
171#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
172#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
173#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
174#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
175
176#define POC_SD3_DS_33V ((uint32_t)1U << 29U)
177#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U)
178#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U)
179#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U)
180#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U)
181#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U)
182#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U)
183#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U)
184#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U)
185#define POC_SD3_CMD_33V ((uint32_t)1U << 20U)
186#define POC_SD3_CLK_33V ((uint32_t)1U << 19U)
187#define POC_SD2_DS_33V ((uint32_t)1U << 18U)
188#define POC_SD2_DAT3_33V ((uint32_t)1U << 17U)
189#define POC_SD2_DAT2_33V ((uint32_t)1U << 16U)
190#define POC_SD2_DAT1_33V ((uint32_t)1U << 15U)
191#define POC_SD2_DAT0_33V ((uint32_t)1U << 14U)
192#define POC_SD2_CMD_33V ((uint32_t)1U << 13U)
193#define POC_SD2_CLK_33V ((uint32_t)1U << 12U)
194#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U)
195#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U)
196#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U)
197#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U)
198#define POC_SD1_CMD_33V ((uint32_t)1U << 7U)
199#define POC_SD1_CLK_33V ((uint32_t)1U << 6U)
200#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U)
201#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U)
202#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U)
203#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U)
204#define POC_SD0_CMD_33V ((uint32_t)1U << 1U)
205#define POC_SD0_CLK_33V ((uint32_t)1U << 0U)
206
207#define DRVCTRL0_MASK (0xCCCCCCCCU)
208#define DRVCTRL1_MASK (0xCCCCCCC8U)
209#define DRVCTRL2_MASK (0x88888888U)
210#define DRVCTRL3_MASK (0x88888888U)
211#define DRVCTRL4_MASK (0x88888888U)
212#define DRVCTRL5_MASK (0x88888888U)
213#define DRVCTRL6_MASK (0x88888888U)
214#define DRVCTRL7_MASK (0x88888888U)
215#define DRVCTRL8_MASK (0x88888888U)
216#define DRVCTRL9_MASK (0x88888888U)
217#define DRVCTRL10_MASK (0x88888888U)
218#define DRVCTRL11_MASK (0x888888CCU)
219#define DRVCTRL12_MASK (0xCCCFFFCFU)
220#define DRVCTRL13_MASK (0xCC888888U)
221#define DRVCTRL14_MASK (0x88888888U)
222#define DRVCTRL15_MASK (0x88888888U)
223#define DRVCTRL16_MASK (0x88888888U)
224#define DRVCTRL17_MASK (0x88888888U)
225#define DRVCTRL18_MASK (0x88888888U)
226#define DRVCTRL19_MASK (0x88888888U)
227#define DRVCTRL20_MASK (0x88888888U)
228#define DRVCTRL21_MASK (0x88888888U)
229#define DRVCTRL22_MASK (0x88888888U)
230#define DRVCTRL23_MASK (0x88888888U)
231#define DRVCTRL24_MASK (0x8888888FU)
232
233#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
234#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
235#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
236#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
237#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
238#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
239#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
240#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
241#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
242#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
243#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
244#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
245#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
246#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
247#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
248#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
249#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
250#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
251#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
252#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
253#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
254#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
255#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
256#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
257#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
258#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
259#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
260#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
261#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
262#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
263#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
264#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
265#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
266#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
267#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
268#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
269#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
270#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
271#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
272#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
273#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
274#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
275#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
276#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
277#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
278#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
279#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
280#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
281#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
282#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
283#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
284#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
285#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
286#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
287#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
288#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
289#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
290#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
291#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
292#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
293#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
294#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
295#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
296#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
297#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
298#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
299#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
300#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
301#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
302#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
303#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
304#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
305#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
306#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
307#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
308#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
309#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
310#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
311#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
312#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
313#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
314#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
315#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
316#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
317#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
318#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
319#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
320#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
321#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
322#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
323#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
324#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
325#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
326#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
327#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
328#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
329#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
330#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
331#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
332#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
333#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
334#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
335#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
336#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
337#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
338#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
339#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
340#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
341#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
342#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
343#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
344#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
345#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
346#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
347#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
348#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
349#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
350#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
351#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
352#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
353#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
354#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
355#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
356#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
357#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
358#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
359#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
360#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
361#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
362#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
363#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
364#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
365#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
366#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
367#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
368#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
369#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
370#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
371#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
372#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
373#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
374#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
375#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
376#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
377#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
378#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
379#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
380#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
381#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
382#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
383#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
384#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
385#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
386#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
387#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
388#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
389#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
390#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
391#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
392#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
393#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
394#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
395#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
396#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
397#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
398#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
399#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
400#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
401#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
402#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
403#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
404#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
405#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
406#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
407#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
408#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
409#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
410#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
411#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
412#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
413#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
414#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
415#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
416#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
417#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
418#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
419#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
420#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
421#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
422#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
423#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
424#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
425#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
426#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
427#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
428
429#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
430#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
431#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
432#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
433#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
434#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
435#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
436#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
437#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
438#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
439#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
440#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
441#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
442#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
443#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
444#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
445#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
446#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
447#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
448#define MOD_SEL0_I2C6_A ((uint32_t)0U << 20U)
449#define MOD_SEL0_I2C6_B ((uint32_t)1U << 20U)
450#define MOD_SEL0_I2C6_C ((uint32_t)2U << 20U)
451#define MOD_SEL0_I2C2_A ((uint32_t)0U << 19U)
452#define MOD_SEL0_I2C2_B ((uint32_t)1U << 19U)
453#define MOD_SEL0_I2C1_A ((uint32_t)0U << 18U)
454#define MOD_SEL0_I2C1_B ((uint32_t)1U << 18U)
455#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 17U)
456#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 17U)
457#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 15U)
458#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 15U)
459#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 15U)
460#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 15U)
461#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 14U)
462#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 14U)
463#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 13U)
464#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 13U)
465#define MOD_SEL0_FSO_A ((uint32_t)0U << 12U)
466#define MOD_SEL0_FSO_B ((uint32_t)1U << 12U)
467#define MOD_SEL0_FM_A ((uint32_t)0U << 11U)
468#define MOD_SEL0_FM_B ((uint32_t)1U << 11U)
469#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 10U)
470#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 10U)
471#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 9U)
472#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 9U)
473#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 8U)
474#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 8U)
475#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 6U)
476#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 6U)
477#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 6U)
478#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 4U)
479#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 4U)
480#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 4U)
481#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 3U)
482#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 3U)
483#define MOD_SEL0_ADG_A ((uint32_t)0U << 1U)
484#define MOD_SEL0_ADG_B ((uint32_t)1U << 1U)
485#define MOD_SEL0_ADG_C ((uint32_t)2U << 1U)
486#define MOD_SEL0_ADG_D ((uint32_t)3U << 1U)
487#define MOD_SEL0_5LINE_A ((uint32_t)0U << 0U)
488#define MOD_SEL0_5LINE_B ((uint32_t)1U << 0U)
489#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
490#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
491#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
492#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
493#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
494#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
495#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
496#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
497#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
498#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
499#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
500#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
501#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
502#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
503#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
504#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
505#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
506#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
507#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
508#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
509#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
510#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
511#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
512#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
513#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
514#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
515#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
516#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
517#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
518#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
519#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
520#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
521#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
522#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
523#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
524#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
525#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
526#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
527#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
528#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
529#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
530#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
531#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
532#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
533#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
534#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
535#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
536#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
537#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
538#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
539#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
540#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
541#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
542#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
543#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
544#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
545#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
546#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
547#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
548#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
549#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
550#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
551#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
552#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
553#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
554
555static void pfc_reg_write(uint32_t addr, uint32_t data);
556
557static void pfc_reg_write(uint32_t addr, uint32_t data)
558{
559 mmio_write_32(PFC_PMMR, ~data);
560 mmio_write_32((uintptr_t) addr, data);
561}
562
563void pfc_init_h3_v1(void)
564{
565 uint32_t reg;
566
567 /* initialize module select */
568 pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
569 | MOD_SEL0_MSIOF2_A
570 | MOD_SEL0_MSIOF1_A
571 | MOD_SEL0_LBSC_A
572 | MOD_SEL0_IEBUS_A
573 | MOD_SEL0_I2C6_A
574 | MOD_SEL0_I2C2_A
575 | MOD_SEL0_I2C1_A
576 | MOD_SEL0_HSCIF4_A
577 | MOD_SEL0_HSCIF3_A
578 | MOD_SEL0_HSCIF2_A
579 | MOD_SEL0_HSCIF1_A
580 | MOD_SEL0_FM_A
581 | MOD_SEL0_ETHERAVB_A
582 | MOD_SEL0_DRIF3_A
583 | MOD_SEL0_DRIF2_A
584 | MOD_SEL0_DRIF1_A
585 | MOD_SEL0_DRIF0_A
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]586 | MOD_SEL0_CANFD0_A
587 | MOD_SEL0_ADG_A
588 | MOD_SEL0_5LINE_A);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]589 pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
590 | MOD_SEL1_TSIF0_A
591 | MOD_SEL1_TIMER_TMU_A
592 | MOD_SEL1_SSP1_1_A
593 | MOD_SEL1_SSP1_0_A
594 | MOD_SEL1_SSI_A
595 | MOD_SEL1_SPEED_PULSE_IF_A
596 | MOD_SEL1_SIMCARD_A
597 | MOD_SEL1_SDHI2_A
598 | MOD_SEL1_SCIF4_A
599 | MOD_SEL1_SCIF3_A
600 | MOD_SEL1_SCIF2_A
601 | MOD_SEL1_SCIF1_A
602 | MOD_SEL1_SCIF_A
603 | MOD_SEL1_REMOCON_A
604 | MOD_SEL1_RCAN0_A
605 | MOD_SEL1_PWM6_A
606 | MOD_SEL1_PWM5_A
607 | MOD_SEL1_PWM4_A
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]608 | MOD_SEL1_PWM3_A
609 | MOD_SEL1_PWM2_A
610 | MOD_SEL1_PWM1_A);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]611 pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]612 | MOD_SEL2_I2C_3_A
613 | MOD_SEL2_I2C_0_A
614 | MOD_SEL2_VIN4_A);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]615
616 /* initialize peripheral function select */
617 pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
618 | IPSR_24_FUNC(0)
619 | IPSR_20_FUNC(0)
620 | IPSR_16_FUNC(0)
621 | IPSR_12_FUNC(0)
622 | IPSR_8_FUNC(0)
623 | IPSR_4_FUNC(0)
624 | IPSR_0_FUNC(0));
625 pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
626 | IPSR_24_FUNC(0)
627 | IPSR_20_FUNC(0)
628 | IPSR_16_FUNC(0)
629 | IPSR_12_FUNC(3)
630 | IPSR_8_FUNC(3)
631 | IPSR_4_FUNC(3)
632 | IPSR_0_FUNC(3));
633 pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
634 | IPSR_24_FUNC(6)
635 | IPSR_20_FUNC(6)
636 | IPSR_16_FUNC(6)
637 | IPSR_12_FUNC(6)
638 | IPSR_8_FUNC(6)
639 | IPSR_4_FUNC(6)
640 | IPSR_0_FUNC(6));
641 pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
642 | IPSR_24_FUNC(6)
643 | IPSR_20_FUNC(6)
644 | IPSR_16_FUNC(6)
645 | IPSR_12_FUNC(6)
646 | IPSR_8_FUNC(0)
647 | IPSR_4_FUNC(0)
648 | IPSR_0_FUNC(0));
649 pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
650 | IPSR_24_FUNC(0)
651 | IPSR_20_FUNC(0)
652 | IPSR_16_FUNC(0)
653 | IPSR_12_FUNC(0)
654 | IPSR_8_FUNC(6)
655 | IPSR_4_FUNC(6)
656 | IPSR_0_FUNC(6));
657 pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
658 | IPSR_24_FUNC(0)
659 | IPSR_20_FUNC(0)
660 | IPSR_16_FUNC(0)
661 | IPSR_12_FUNC(0)
662 | IPSR_8_FUNC(6)
663 | IPSR_4_FUNC(0)
664 | IPSR_0_FUNC(0));
665 pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
666 | IPSR_24_FUNC(6)
667 | IPSR_20_FUNC(6)
668 | IPSR_16_FUNC(6)
669 | IPSR_12_FUNC(6)
670 | IPSR_8_FUNC(0)
671 | IPSR_4_FUNC(0)
672 | IPSR_0_FUNC(0));
673 pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
674 | IPSR_24_FUNC(0)
675 | IPSR_20_FUNC(0)
676 | IPSR_16_FUNC(0)
677 | IPSR_12_FUNC(0)
678 | IPSR_8_FUNC(6)
679 | IPSR_4_FUNC(6)
680 | IPSR_0_FUNC(6));
681 pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
682 | IPSR_24_FUNC(1)
683 | IPSR_20_FUNC(1)
684 | IPSR_16_FUNC(1)
685 | IPSR_12_FUNC(0)
686 | IPSR_8_FUNC(0)
687 | IPSR_4_FUNC(0)
688 | IPSR_0_FUNC(0));
689 pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
690 | IPSR_24_FUNC(0)
691 | IPSR_20_FUNC(0)
692 | IPSR_16_FUNC(0)
693 | IPSR_12_FUNC(0)
694 | IPSR_8_FUNC(0)
695 | IPSR_4_FUNC(0)
696 | IPSR_0_FUNC(0));
697 pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)
698 | IPSR_24_FUNC(4)
699 | IPSR_20_FUNC(0)
700 | IPSR_16_FUNC(0)
701 | IPSR_12_FUNC(0)
702 | IPSR_8_FUNC(0)
703 | IPSR_4_FUNC(1)
704 | IPSR_0_FUNC(1));
705 pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
706 | IPSR_24_FUNC(0)
707 | IPSR_20_FUNC(0)
708 | IPSR_16_FUNC(0)
709 | IPSR_12_FUNC(0)
710 | IPSR_8_FUNC(4)
711 | IPSR_4_FUNC(0)
712 | IPSR_0_FUNC(0));
713 pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(8)
714 | IPSR_24_FUNC(0)
715 | IPSR_20_FUNC(0)
716 | IPSR_16_FUNC(0)
717 | IPSR_12_FUNC(0)
718 | IPSR_8_FUNC(3)
719 | IPSR_4_FUNC(0)
720 | IPSR_0_FUNC(0));
721 pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
722 | IPSR_24_FUNC(0)
723 | IPSR_20_FUNC(0)
724 | IPSR_16_FUNC(0)
725 | IPSR_12_FUNC(0)
726 | IPSR_8_FUNC(0)
727 | IPSR_4_FUNC(3)
728 | IPSR_0_FUNC(8));
729 pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
730 | IPSR_24_FUNC(0)
731 | IPSR_20_FUNC(0)
732 | IPSR_16_FUNC(0)
733 | IPSR_12_FUNC(0)
734 | IPSR_8_FUNC(0)
735 | IPSR_4_FUNC(0)
736 | IPSR_0_FUNC(0));
737 pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
738 | IPSR_24_FUNC(0)
739 | IPSR_20_FUNC(0)
740 | IPSR_16_FUNC(0)
741 | IPSR_12_FUNC(0)
742 | IPSR_8_FUNC(0)
743 | IPSR_4_FUNC(1)
744 | IPSR_0_FUNC(1));
745 pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
746 | IPSR_24_FUNC(0)
747 | IPSR_20_FUNC(0)
748 | IPSR_16_FUNC(0)
749 | IPSR_12_FUNC(0)
750 | IPSR_8_FUNC(0)
751 | IPSR_4_FUNC(1)
752 | IPSR_0_FUNC(0));
753 pfc_reg_write(PFC_IPSR17, IPSR_4_FUNC(0)
754 | IPSR_0_FUNC(0));
755
756 /* initialize GPIO/perihperal function select */
757 pfc_reg_write(PFC_GPSR0, GPSR0_D15
758 | GPSR0_D14
759 | GPSR0_D13
760 | GPSR0_D12
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]761 | GPSR0_D11
762 | GPSR0_D10
763 | GPSR0_D9
764 | GPSR0_D8);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]765 pfc_reg_write(PFC_GPSR1, GPSR1_EX_WAIT0_A
766 | GPSR1_A19
767 | GPSR1_A18
768 | GPSR1_A17
769 | GPSR1_A16
770 | GPSR1_A15
771 | GPSR1_A14
772 | GPSR1_A13
773 | GPSR1_A12
774 | GPSR1_A7
775 | GPSR1_A6
776 | GPSR1_A5
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]777 | GPSR1_A4
778 | GPSR1_A3
779 | GPSR1_A2
780 | GPSR1_A1
781 | GPSR1_A0);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]782 pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
783 | GPSR2_AVB_AVTP_MATCH_A
784 | GPSR2_AVB_LINK
785 | GPSR2_AVB_PHY_INT
786 | GPSR2_AVB_MDC
787 | GPSR2_PWM2_A
788 | GPSR2_PWM1_A
789 | GPSR2_IRQ5
790 | GPSR2_IRQ4
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]791 | GPSR2_IRQ3
792 | GPSR2_IRQ2
793 | GPSR2_IRQ1
794 | GPSR2_IRQ0);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]795 pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
796 | GPSR3_SD0_CD
797 | GPSR3_SD1_DAT3
798 | GPSR3_SD1_DAT2
799 | GPSR3_SD1_DAT1
800 | GPSR3_SD1_DAT0
801 | GPSR3_SD0_DAT3
802 | GPSR3_SD0_DAT2
803 | GPSR3_SD0_DAT1
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]804 | GPSR3_SD0_DAT0
805 | GPSR3_SD0_CMD
806 | GPSR3_SD0_CLK);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]807 pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
808 | GPSR4_SD3_DAT6
809 | GPSR4_SD3_DAT3
810 | GPSR4_SD3_DAT2
811 | GPSR4_SD3_DAT1
812 | GPSR4_SD3_DAT0
813 | GPSR4_SD3_CMD
814 | GPSR4_SD3_CLK
815 | GPSR4_SD2_DS
816 | GPSR4_SD2_DAT3
817 | GPSR4_SD2_DAT2
818 | GPSR4_SD2_DAT1
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]819 | GPSR4_SD2_DAT0
820 | GPSR4_SD2_CMD
821 | GPSR4_SD2_CLK);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]822 pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
823 | GPSR5_MSIOF0_SS1
824 | GPSR5_MSIOF0_SYNC
825 | GPSR5_HRTS0
826 | GPSR5_HCTS0
827 | GPSR5_HTX0
828 | GPSR5_HRX0
829 | GPSR5_HSCK0
830 | GPSR5_RX2_A
831 | GPSR5_TX2_A
832 | GPSR5_SCK2
833 | GPSR5_RTS1_TANS
834 | GPSR5_CTS1
835 | GPSR5_TX1_A
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]836 | GPSR5_RX1_A
837 | GPSR5_RTS0_TANS
838 | GPSR5_SCK0);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]839 pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
840 | GPSR6_USB30_PWEN
841 | GPSR6_USB1_OVC
842 | GPSR6_USB1_PWEN
843 | GPSR6_USB0_OVC
844 | GPSR6_USB0_PWEN
845 | GPSR6_AUDIO_CLKB_B
846 | GPSR6_AUDIO_CLKA_A
847 | GPSR6_SSI_SDATA8
848 | GPSR6_SSI_SDATA7
849 | GPSR6_SSI_WS78
850 | GPSR6_SSI_SCK78
851 | GPSR6_SSI_WS6
852 | GPSR6_SSI_SCK6
853 | GPSR6_SSI_SDATA4
854 | GPSR6_SSI_WS4
855 | GPSR6_SSI_SCK4
856 | GPSR6_SSI_SDATA1_A
857 | GPSR6_SSI_SDATA0
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]858 | GPSR6_SSI_WS0129
859 | GPSR6_SSI_SCK0129);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]860 pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]861 | GPSR7_HDMI0_CEC
862 | GPSR7_AVS2
863 | GPSR7_AVS1);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]864
865 /* initialize POC control register */
866 pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
867 | POC_SD3_DAT7_33V
868 | POC_SD3_DAT6_33V
869 | POC_SD3_DAT5_33V
870 | POC_SD3_DAT4_33V
871 | POC_SD3_DAT3_33V
872 | POC_SD3_DAT2_33V
873 | POC_SD3_DAT1_33V
874 | POC_SD3_DAT0_33V
875 | POC_SD3_CMD_33V
876 | POC_SD3_CLK_33V
877 | POC_SD0_DAT3_33V
878 | POC_SD0_DAT2_33V
879 | POC_SD0_DAT1_33V
Marek Vasutbda11cb2018-12-12 17:40:10 +0100[diff] [blame]880 | POC_SD0_DAT0_33V
881 | POC_SD0_CMD_33V
882 | POC_SD0_CLK_33V);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]883
884 /* initialize DRV control register */
885 reg = mmio_read_32(PFC_DRVCTRL0);
886 reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
887 | DRVCTRL0_QSPI0_MOSI_IO0(3)
888 | DRVCTRL0_QSPI0_MISO_IO1(3)
889 | DRVCTRL0_QSPI0_IO2(3)
890 | DRVCTRL0_QSPI0_IO3(3)
891 | DRVCTRL0_QSPI0_SSL(3)
892 | DRVCTRL0_QSPI1_SPCLK(3)
893 | DRVCTRL0_QSPI1_MOSI_IO0(3));
894 pfc_reg_write(PFC_DRVCTRL0, reg);
895 reg = mmio_read_32(PFC_DRVCTRL1);
896 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
897 | DRVCTRL1_QSPI1_IO2(3)
898 | DRVCTRL1_QSPI1_IO3(3)
899 | DRVCTRL1_QSPI1_SS(3)
900 | DRVCTRL1_RPC_INT(3)
901 | DRVCTRL1_RPC_WP(3)
902 | DRVCTRL1_RPC_RESET(3)
903 | DRVCTRL1_AVB_RX_CTL(7));
904 pfc_reg_write(PFC_DRVCTRL1, reg);
905 reg = mmio_read_32(PFC_DRVCTRL2);
906 reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
907 | DRVCTRL2_AVB_RD0(7)
908 | DRVCTRL2_AVB_RD1(7)
909 | DRVCTRL2_AVB_RD2(7)
910 | DRVCTRL2_AVB_RD3(7)
911 | DRVCTRL2_AVB_TX_CTL(3)
912 | DRVCTRL2_AVB_TXC(3)
913 | DRVCTRL2_AVB_TD0(3));
914 pfc_reg_write(PFC_DRVCTRL2, reg);
915 reg = mmio_read_32(PFC_DRVCTRL3);
916 reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
917 | DRVCTRL3_AVB_TD2(3)
918 | DRVCTRL3_AVB_TD3(3)
919 | DRVCTRL3_AVB_TXCREFCLK(7)
920 | DRVCTRL3_AVB_MDIO(7)
921 | DRVCTRL3_AVB_MDC(7)
922 | DRVCTRL3_AVB_MAGIC(7)
923 | DRVCTRL3_AVB_PHY_INT(7));
924 pfc_reg_write(PFC_DRVCTRL3, reg);
925 reg = mmio_read_32(PFC_DRVCTRL4);
926 reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
927 | DRVCTRL4_AVB_AVTP_MATCH(7)
928 | DRVCTRL4_AVB_AVTP_CAPTURE(7)
929 | DRVCTRL4_IRQ0(7)
930 | DRVCTRL4_IRQ1(7)
931 | DRVCTRL4_IRQ2(7)
932 | DRVCTRL4_IRQ3(7)
933 | DRVCTRL4_IRQ4(7));
934 pfc_reg_write(PFC_DRVCTRL4, reg);
935 reg = mmio_read_32(PFC_DRVCTRL5);
936 reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
937 | DRVCTRL5_PWM0(7)
938 | DRVCTRL5_PWM1(7)
939 | DRVCTRL5_PWM2(7)
940 | DRVCTRL5_A0(3)
941 | DRVCTRL5_A1(3)
942 | DRVCTRL5_A2(3)
943 | DRVCTRL5_A3(3));
944 pfc_reg_write(PFC_DRVCTRL5, reg);
945 reg = mmio_read_32(PFC_DRVCTRL6);
946 reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
947 | DRVCTRL6_A5(3)
948 | DRVCTRL6_A6(3)
949 | DRVCTRL6_A7(3)
950 | DRVCTRL6_A8(7)
951 | DRVCTRL6_A9(7)
952 | DRVCTRL6_A10(7)
953 | DRVCTRL6_A11(7));
954 pfc_reg_write(PFC_DRVCTRL6, reg);
955 reg = mmio_read_32(PFC_DRVCTRL7);
956 reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
957 | DRVCTRL7_A13(3)
958 | DRVCTRL7_A14(3)
959 | DRVCTRL7_A15(3)
960 | DRVCTRL7_A16(3)
961 | DRVCTRL7_A17(3)
962 | DRVCTRL7_A18(3)
963 | DRVCTRL7_A19(3));
964 pfc_reg_write(PFC_DRVCTRL7, reg);
965 reg = mmio_read_32(PFC_DRVCTRL8);
966 reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
967 | DRVCTRL8_CS0(7)
968 | DRVCTRL8_CS1_A2(7)
969 | DRVCTRL8_BS(7)
970 | DRVCTRL8_RD(7)
971 | DRVCTRL8_RD_W(7)
972 | DRVCTRL8_WE0(7)
973 | DRVCTRL8_WE1(7));
974 pfc_reg_write(PFC_DRVCTRL8, reg);
975 reg = mmio_read_32(PFC_DRVCTRL9);
976 reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
977 | DRVCTRL9_PRESETOU(7)
978 | DRVCTRL9_D0(7)
979 | DRVCTRL9_D1(7)
980 | DRVCTRL9_D2(7)
981 | DRVCTRL9_D3(7)
982 | DRVCTRL9_D4(7)
983 | DRVCTRL9_D5(7));
984 pfc_reg_write(PFC_DRVCTRL9, reg);
985 reg = mmio_read_32(PFC_DRVCTRL10);
986 reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
987 | DRVCTRL10_D7(7)
988 | DRVCTRL10_D8(3)
989 | DRVCTRL10_D9(3)
990 | DRVCTRL10_D10(3)
991 | DRVCTRL10_D11(3)
992 | DRVCTRL10_D12(3)
993 | DRVCTRL10_D13(3));
994 pfc_reg_write(PFC_DRVCTRL10, reg);
995 reg = mmio_read_32(PFC_DRVCTRL11);
996 reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
997 | DRVCTRL11_D15(3)
998 | DRVCTRL11_AVS1(7)
999 | DRVCTRL11_AVS2(7)
1000 | DRVCTRL11_HDMI0_CEC(7)
1001 | DRVCTRL11_HDMI1_CEC(7)
1002 | DRVCTRL11_DU_DOTCLKIN0(3)
1003 | DRVCTRL11_DU_DOTCLKIN1(3));
1004 pfc_reg_write(PFC_DRVCTRL11, reg);
1005 reg = mmio_read_32(PFC_DRVCTRL12);
1006 reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
1007 | DRVCTRL12_DU_DOTCLKIN3(3)
1008 | DRVCTRL12_DU_FSCLKST(3)
1009 | DRVCTRL12_DU_TMS(3));
1010 pfc_reg_write(PFC_DRVCTRL12, reg);
1011 reg = mmio_read_32(PFC_DRVCTRL13);
1012 reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
1013 | DRVCTRL13_ASEBRK(3)
1014 | DRVCTRL13_SD0_CLK(2)
1015 | DRVCTRL13_SD0_CMD(2)
1016 | DRVCTRL13_SD0_DAT0(2)
1017 | DRVCTRL13_SD0_DAT1(2)
1018 | DRVCTRL13_SD0_DAT2(2)
1019 | DRVCTRL13_SD0_DAT3(2));
1020 pfc_reg_write(PFC_DRVCTRL13, reg);
1021 reg = mmio_read_32(PFC_DRVCTRL14);
1022 reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
1023 | DRVCTRL14_SD1_CMD(7)
1024 | DRVCTRL14_SD1_DAT0(5)
1025 | DRVCTRL14_SD1_DAT1(5)
1026 | DRVCTRL14_SD1_DAT2(5)
1027 | DRVCTRL14_SD1_DAT3(5)
1028 | DRVCTRL14_SD2_CLK(5)
1029 | DRVCTRL14_SD2_CMD(5));
1030 pfc_reg_write(PFC_DRVCTRL14, reg);
1031 reg = mmio_read_32(PFC_DRVCTRL15);
1032 reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
1033 | DRVCTRL15_SD2_DAT1(5)
1034 | DRVCTRL15_SD2_DAT2(5)
1035 | DRVCTRL15_SD2_DAT3(5)
1036 | DRVCTRL15_SD2_DS(5)
1037 | DRVCTRL15_SD3_CLK(2)
1038 | DRVCTRL15_SD3_CMD(2)
1039 | DRVCTRL15_SD3_DAT0(2));
1040 pfc_reg_write(PFC_DRVCTRL15, reg);
1041 reg = mmio_read_32(PFC_DRVCTRL16);
1042 reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(2)
1043 | DRVCTRL16_SD3_DAT2(2)
1044 | DRVCTRL16_SD3_DAT3(2)
1045 | DRVCTRL16_SD3_DAT4(7)
1046 | DRVCTRL16_SD3_DAT5(7)
1047 | DRVCTRL16_SD3_DAT6(7)
1048 | DRVCTRL16_SD3_DAT7(7)
1049 | DRVCTRL16_SD3_DS(7));
1050 pfc_reg_write(PFC_DRVCTRL16, reg);
1051 reg = mmio_read_32(PFC_DRVCTRL17);
1052 reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
1053 | DRVCTRL17_SD0_WP(7)
1054 | DRVCTRL17_SD1_CD(7)
1055 | DRVCTRL17_SD1_WP(7)
1056 | DRVCTRL17_SCK0(7)
1057 | DRVCTRL17_RX0(7)
1058 | DRVCTRL17_TX0(7)
1059 | DRVCTRL17_CTS0(7));
1060 pfc_reg_write(PFC_DRVCTRL17, reg);
1061 reg = mmio_read_32(PFC_DRVCTRL18);
1062 reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
1063 | DRVCTRL18_RX1(7)
1064 | DRVCTRL18_TX1(7)
1065 | DRVCTRL18_CTS1(7)
1066 | DRVCTRL18_RTS1_TANS(7)
1067 | DRVCTRL18_SCK2(7)
1068 | DRVCTRL18_TX2(7)
1069 | DRVCTRL18_RX2(7));
1070 pfc_reg_write(PFC_DRVCTRL18, reg);
1071 reg = mmio_read_32(PFC_DRVCTRL19);
1072 reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
1073 | DRVCTRL19_HRX0(7)
1074 | DRVCTRL19_HTX0(7)
1075 | DRVCTRL19_HCTS0(7)
1076 | DRVCTRL19_HRTS0(7)
1077 | DRVCTRL19_MSIOF0_SCK(7)
1078 | DRVCTRL19_MSIOF0_SYNC(7)
1079 | DRVCTRL19_MSIOF0_SS1(7));
1080 pfc_reg_write(PFC_DRVCTRL19, reg);
1081 reg = mmio_read_32(PFC_DRVCTRL20);
1082 reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
1083 | DRVCTRL20_MSIOF0_SS2(7)
1084 | DRVCTRL20_MSIOF0_RXD(7)
1085 | DRVCTRL20_MLB_CLK(7)
1086 | DRVCTRL20_MLB_SIG(7)
1087 | DRVCTRL20_MLB_DAT(7)
1088 | DRVCTRL20_MLB_REF(7)
1089 | DRVCTRL20_SSI_SCK0129(7));
1090 pfc_reg_write(PFC_DRVCTRL20, reg);
1091 reg = mmio_read_32(PFC_DRVCTRL21);
1092 reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
1093 | DRVCTRL21_SSI_SDATA0(7)
1094 | DRVCTRL21_SSI_SDATA1(7)
1095 | DRVCTRL21_SSI_SDATA2(7)
1096 | DRVCTRL21_SSI_SCK34(7)
1097 | DRVCTRL21_SSI_WS34(7)
1098 | DRVCTRL21_SSI_SDATA3(7)
1099 | DRVCTRL21_SSI_SCK4(7));
1100 pfc_reg_write(PFC_DRVCTRL21, reg);
1101 reg = mmio_read_32(PFC_DRVCTRL22);
1102 reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
1103 | DRVCTRL22_SSI_SDATA4(7)
1104 | DRVCTRL22_SSI_SCK5(7)
1105 | DRVCTRL22_SSI_WS5(7)
1106 | DRVCTRL22_SSI_SDATA5(7)
1107 | DRVCTRL22_SSI_SCK6(7)
1108 | DRVCTRL22_SSI_WS6(7)
1109 | DRVCTRL22_SSI_SDATA6(7));
1110 pfc_reg_write(PFC_DRVCTRL22, reg);
1111 reg = mmio_read_32(PFC_DRVCTRL23);
1112 reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
1113 | DRVCTRL23_SSI_WS78(7)
1114 | DRVCTRL23_SSI_SDATA7(7)
1115 | DRVCTRL23_SSI_SDATA8(7)
1116 | DRVCTRL23_SSI_SDATA9(7)
1117 | DRVCTRL23_AUDIO_CLKA(7)
1118 | DRVCTRL23_AUDIO_CLKB(7)
1119 | DRVCTRL23_USB0_PWEN(7));
1120 pfc_reg_write(PFC_DRVCTRL23, reg);
1121 reg = mmio_read_32(PFC_DRVCTRL24);
1122 reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
1123 | DRVCTRL24_USB1_PWEN(7)
1124 | DRVCTRL24_USB1_OVC(7)
1125 | DRVCTRL24_USB30_PWEN(7)
1126 | DRVCTRL24_USB30_OVC(7)
1127 | DRVCTRL24_USB31_PWEN(7)
1128 | DRVCTRL24_USB31_OVC(7));
1129 pfc_reg_write(PFC_DRVCTRL24, reg);
1130
1131 /* initialize LSI pin pull-up/down control */
1132 pfc_reg_write(PFC_PUD0, 0x00005FBFU);
1133 pfc_reg_write(PFC_PUD1, 0x00300FFEU);
1134 pfc_reg_write(PFC_PUD2, 0x330001E6U);
1135 pfc_reg_write(PFC_PUD3, 0x000002E0U);
1136 pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
1137 pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
1138 pfc_reg_write(PFC_PUD6, 0x00000055U);
1139
1140 /* initialize LSI pin pull-enable register */
1141 pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
1142 pfc_reg_write(PFC_PUEN1, 0x00100234U);
1143 pfc_reg_write(PFC_PUEN2, 0x000004C4U);
1144 pfc_reg_write(PFC_PUEN3, 0x00000200U);
1145 pfc_reg_write(PFC_PUEN4, 0x3E000000U);
1146 pfc_reg_write(PFC_PUEN5, 0x1F000805U);
1147 pfc_reg_write(PFC_PUEN6, 0x00000006U);
1148
1149 /* initialize positive/negative logic select */
1150 mmio_write_32(GPIO_POSNEG0, 0x00000000U);
1151 mmio_write_32(GPIO_POSNEG1, 0x00000000U);
1152 mmio_write_32(GPIO_POSNEG2, 0x00000000U);
1153 mmio_write_32(GPIO_POSNEG3, 0x00000000U);
1154 mmio_write_32(GPIO_POSNEG4, 0x00000000U);
1155 mmio_write_32(GPIO_POSNEG5, 0x00000000U);
1156 mmio_write_32(GPIO_POSNEG6, 0x00000000U);
1157
1158 /* initialize general IO/interrupt switching */
1159 mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
1160 mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
1161 mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
1162 mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
1163 mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
1164 mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
1165 mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
1166
1167 /* initialize general output register */
1168 mmio_write_32(GPIO_OUTDT1, 0x00000000U);
1169 mmio_write_32(GPIO_OUTDT2, 0x00000400U);
1170 mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
1171 mmio_write_32(GPIO_OUTDT5, 0x00000006U);
1172 mmio_write_32(GPIO_OUTDT6, 0x00003880U);
1173
1174 /* initialize general input/output switching */
1175 mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
1176 mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
1177 mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
1178 mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
1179 mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
Marek Vasut06302992019-03-02 15:34:36 +0100[diff] [blame]1180#if (RCAR_GEN3_ULCB == 1)
1181 mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
1182#else
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1183 mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
Marek Vasut06302992019-03-02 15:34:36 +0100[diff] [blame]1184#endif
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1185 mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
1186}