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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Roberto Vargas2ca18d92018-02-12 12:36:17 +00002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arm_def.h>
Antonio Nino Diaz7289f922017-11-09 11:34:09 +00008#include <arm_spm_def.h>
Dan Handley9df48042015-03-19 18:58:55 +00009#include <debug.h>
Roberto Vargas2ca18d92018-02-12 12:36:17 +000010#include <plat_arm.h>
Dan Handley9df48042015-03-19 18:58:55 +000011#include <platform_def.h>
12#include <tzc400.h>
13
14
15/* Weak definitions may be overridden in specific ARM standard platform */
16#pragma weak plat_arm_security_setup
17
18
19/*******************************************************************************
20 * Initialize the TrustZone Controller for ARM standard platforms.
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000021 * When booting an EL3 payload, this is simplified: we configure region 0 with
22 * secure access only and do not enable any other region.
Dan Handley9df48042015-03-19 18:58:55 +000023 ******************************************************************************/
Summer Qin5ce394c2018-03-12 11:28:26 +080024void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions)
Dan Handley9df48042015-03-19 18:58:55 +000025{
Summer Qin5ce394c2018-03-12 11:28:26 +080026#ifndef EL3_PAYLOAD_BASE
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010027 unsigned int region_index = 1U;
Summer Qin5ce394c2018-03-12 11:28:26 +080028 const arm_tzc_regions_info_t *p;
29 const arm_tzc_regions_info_t init_tzc_regions[] = {
30 ARM_TZC_REGIONS_DEF,
31 {0}
32 };
33#endif
34
Dan Handley9df48042015-03-19 18:58:55 +000035 INFO("Configuring TrustZone Controller\n");
36
Soby Mathew9c708b52016-02-26 14:23:19 +000037 tzc400_init(PLAT_ARM_TZC_BASE);
Dan Handley9df48042015-03-19 18:58:55 +000038
39 /* Disable filters. */
Soby Mathew9c708b52016-02-26 14:23:19 +000040 tzc400_disable_filters();
Dan Handley9df48042015-03-19 18:58:55 +000041
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000042#ifndef EL3_PAYLOAD_BASE
Summer Qin5ce394c2018-03-12 11:28:26 +080043 if (tzc_regions == NULL)
44 p = init_tzc_regions;
45 else
46 p = tzc_regions;
Soby Mathew7e4d6652017-05-10 11:50:30 +010047
Dan Handley9df48042015-03-19 18:58:55 +000048 /* Region 0 set to no access by default */
Soby Mathew9c708b52016-02-26 14:23:19 +000049 tzc400_configure_region0(TZC_REGION_S_NONE, 0);
Dan Handley9df48042015-03-19 18:58:55 +000050
Summer Qin5ce394c2018-03-12 11:28:26 +080051 /* Rest Regions set according to tzc_regions array */
52 for (; p->base != 0ULL; p++) {
53 tzc400_configure_region(PLAT_ARM_TZC_FILTERS, region_index,
54 p->base, p->end, p->sec_attr, p->nsaid_permissions);
55 region_index++;
56 }
Dan Handley9df48042015-03-19 18:58:55 +000057
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010058 INFO("Total %u regions set.\n", region_index);
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000059
60#else /* if defined(EL3_PAYLOAD_BASE) */
61
Soby Mathew15b149e2017-11-13 08:29:45 +000062 /* Allow Secure and Non-secure access to DRAM for EL3 payloads */
63 tzc400_configure_region0(TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS);
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000064
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000065#endif /* EL3_PAYLOAD_BASE */
Dan Handley9df48042015-03-19 18:58:55 +000066
67 /*
68 * Raise an exception if a NS device tries to access secure memory
69 * TODO: Add interrupt handling support.
70 */
Soby Mathew9c708b52016-02-26 14:23:19 +000071 tzc400_set_action(TZC_ACTION_ERR);
Dan Handley9df48042015-03-19 18:58:55 +000072
73 /* Enable filters. */
Soby Mathew9c708b52016-02-26 14:23:19 +000074 tzc400_enable_filters();
Dan Handley9df48042015-03-19 18:58:55 +000075}
76
77void plat_arm_security_setup(void)
78{
Summer Qin5ce394c2018-03-12 11:28:26 +080079 arm_tzc400_setup(NULL);
Dan Handley9df48042015-03-19 18:58:55 +000080}