Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <mmio.h> |
| 8 | #include <debug.h> |
| 9 | #include "dram_sub_func.h" |
| 10 | |
| 11 | #define PRR (0xFFF00044U) |
| 12 | #define PRR_PRODUCT_MASK (0x00007F00U) |
| 13 | #define PRR_CUT_MASK (0x000000FFU) |
| 14 | #define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ |
| 15 | #define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ |
| 16 | #define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ |
| 17 | #define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */ |
| 18 | #define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */ |
| 19 | |
| 20 | #if RCAR_SYSTEM_SUSPEND |
| 21 | #include "iic_dvfs.h" |
| 22 | |
| 23 | #define DRAM_BACKUP_GPIO_USE (0) |
| 24 | #if PMIC_ROHM_BD9571 |
| 25 | #define PMIC_BKUP_MODE_CNT (0x20U) |
| 26 | #define PMIC_QLLM_CNT (0x27U) |
| 27 | #define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4U)) |
| 28 | #define BIT_QLLM_DDR0_EN ((uint8_t)(1U << 0U)) |
| 29 | #define BIT_QLLM_DDR1_EN ((uint8_t)(1U << 1U)) |
| 30 | #endif |
| 31 | |
| 32 | #define GPIO_OUTDT1 (0xE6051008U) |
| 33 | #define GPIO_INDT1 (0xE605100CU) |
| 34 | #define GPIO_OUTDT3 (0xE6053008U) |
| 35 | #define GPIO_INDT3 (0xE605300CU) |
| 36 | #define GPIO_OUTDT6 (0xE6055408U) |
| 37 | #define GPIO_INDT6 (0xE605540CU) |
| 38 | |
| 39 | #if DRAM_BACKUP_GPIO_USE == 1 |
| 40 | #define GPIO_BKUP_REQB_SHIFT_SALVATOR (9U) /* GP1_9 (BKUP_REQB) */ |
| 41 | #define GPIO_BKUP_REQB_SHIFT_EBISU (14U) /* GP6_14(BKUP_REQB) */ |
| 42 | #define GPIO_BKUP_REQB_SHIFT_CONDOR (1U) /* GP3_1 (BKUP_REQB) */ |
| 43 | #endif |
| 44 | #define GPIO_BKUP_TRG_SHIFT_SALVATOR (8U) /* GP1_8 (BKUP_TRG) */ |
| 45 | #define GPIO_BKUP_TRG_SHIFT_EBISU (13U) /* GP6_13(BKUP_TRG) */ |
| 46 | #define GPIO_BKUP_TRG_SHIFT_CONDOR (0U) /* GP3_0 (BKUP_TRG) */ |
| 47 | |
| 48 | #define DRAM_BKUP_TRG_LOOP_CNT (1000U) |
| 49 | #endif |
| 50 | |
| 51 | void rcar_dram_get_boot_status(uint32_t * status) |
| 52 | { |
| 53 | #if RCAR_SYSTEM_SUSPEND |
| 54 | uint32_t shift = GPIO_BKUP_TRG_SHIFT_SALVATOR; |
| 55 | uint32_t gpio = GPIO_INDT1; |
| 56 | uint32_t reg, product; |
| 57 | |
| 58 | product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; |
| 59 | |
| 60 | if (product == PRR_PRODUCT_V3H) { |
| 61 | shift = GPIO_BKUP_TRG_SHIFT_CONDOR; |
| 62 | gpio = GPIO_INDT3; |
| 63 | } else if (product == PRR_PRODUCT_E3) { |
| 64 | shift = GPIO_BKUP_TRG_SHIFT_EBISU; |
| 65 | gpio = GPIO_INDT6; |
| 66 | } |
| 67 | |
| 68 | reg = mmio_read_32(gpio) & (1U << shift); |
| 69 | *status = reg ? DRAM_BOOT_STATUS_WARM : DRAM_BOOT_STATUS_COLD; |
| 70 | #else |
| 71 | *status = DRAM_BOOT_STATUS_COLD; |
| 72 | #endif |
| 73 | } |
| 74 | |
| 75 | int32_t rcar_dram_update_boot_status(uint32_t status) |
| 76 | { |
| 77 | int32_t ret = 0; |
| 78 | #if RCAR_SYSTEM_SUSPEND |
| 79 | #if PMIC_ROHM_BD9571 |
| 80 | #if DRAM_BACKUP_GPIO_USE == 0 |
| 81 | uint8_t mode = 0U; |
| 82 | #else |
| 83 | uint32_t reqb, outd; |
| 84 | #endif |
| 85 | uint8_t qllm = 0; |
| 86 | #endif |
| 87 | uint32_t i, product, trg, gpio; |
| 88 | |
| 89 | product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; |
| 90 | if (product == PRR_PRODUCT_V3H) { |
| 91 | #if DRAM_BACKUP_GPIO_USE == 1 |
| 92 | reqb = GPIO_BKUP_REQB_SHIFT_CONDOR; |
| 93 | outd = GPIO_OUTDT3; |
| 94 | #endif |
| 95 | trg = GPIO_BKUP_TRG_SHIFT_CONDOR; |
| 96 | gpio = GPIO_INDT3; |
| 97 | } else if (product == PRR_PRODUCT_E3) { |
| 98 | #if DRAM_BACKUP_GPIO_USE == 1 |
| 99 | reqb = GPIO_BKUP_REQB_SHIFT_EBISU; |
| 100 | outd = GPIO_OUTDT6; |
| 101 | #endif |
| 102 | trg = GPIO_BKUP_TRG_SHIFT_EBISU; |
| 103 | gpio = GPIO_INDT6; |
| 104 | } else { |
| 105 | #if DRAM_BACKUP_GPIO_USE == 1 |
| 106 | reqb = GPIO_BKUP_REQB_SHIFT_SALVATOR; |
| 107 | outd = GPIO_OUTDT1; |
| 108 | #endif |
| 109 | trg = GPIO_BKUP_TRG_SHIFT_SALVATOR; |
| 110 | gpio = GPIO_INDT1; |
| 111 | } |
| 112 | |
| 113 | if (status != DRAM_BOOT_STATUS_WARM) |
| 114 | goto cold; |
| 115 | |
| 116 | #if DRAM_BACKUP_GPIO_USE==1 |
| 117 | mmio_setbits_32(outd, 1U << reqb); |
| 118 | #else |
| 119 | |
| 120 | #if PMIC_ROHM_BD9571 |
| 121 | if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode)) { |
| 122 | ERROR("BKUP mode cnt READ ERROR.\n"); |
| 123 | return DRAM_UPDATE_STATUS_ERR; |
| 124 | } |
| 125 | |
| 126 | mode &= ~BIT_BKUP_CTRL_OUT; |
| 127 | if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode)) { |
| 128 | ERROR("BKUP mode cnt WRITE ERROR. value = %d\n", mode); |
| 129 | return DRAM_UPDATE_STATUS_ERR; |
| 130 | } |
| 131 | #endif |
| 132 | #endif |
| 133 | for (i = 0; i < DRAM_BKUP_TRG_LOOP_CNT; i++) { |
| 134 | if (mmio_read_32(gpio) & (1U << trg)) |
| 135 | continue; |
| 136 | |
| 137 | goto cold; |
| 138 | } |
| 139 | |
| 140 | ERROR("\nWarm booting Error...\n" |
| 141 | " The potential of BKUP_TRG did not switch " |
| 142 | "to Low.\n If you expect the operation of " |
| 143 | "cold boot,\n check the board configuration" |
| 144 | " (ex, Dip-SW) and/or the H/W failure.\n"); |
| 145 | |
| 146 | return DRAM_UPDATE_STATUS_ERR; |
| 147 | |
| 148 | cold: |
| 149 | #if PMIC_ROHM_BD9571 |
| 150 | if (ret) |
| 151 | return ret; |
| 152 | |
| 153 | qllm = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN); |
| 154 | if (rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, qllm)) { |
| 155 | ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm); |
| 156 | ret = DRAM_UPDATE_STATUS_ERR; |
| 157 | } |
| 158 | #endif |
| 159 | #endif |
| 160 | return ret; |
| 161 | } |