Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 9 | |
| 10 | #include <arm_def.h> |
| 11 | #include <board_arm_def.h> |
| 12 | #include <board_css_def.h> |
| 13 | #include <common_def.h> |
| 14 | #include <css_def.h> |
| 15 | #include <soc_css_def.h> |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 16 | #include <utils_def.h> |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 17 | |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 18 | #define CSS_SGI_MAX_CPUS_PER_CLUSTER 4 |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 19 | |
| 20 | /* CPU topology */ |
| 21 | #define PLAT_ARM_CLUSTER_COUNT 2 |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 22 | #define CSS_SGI_MAX_PE_PER_CPU 1 |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 23 | #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 24 | CSS_SGI_MAX_CPUS_PER_CLUSTER * \ |
| 25 | CSS_SGI_MAX_PE_PER_CPU) |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 26 | |
| 27 | #if ARM_BOARD_OPTIMISE_MEM |
| 28 | |
| 29 | #if defined(IMAGE_BL31) || defined(IMAGE_BL32) |
| 30 | # define PLAT_ARM_MMAP_ENTRIES 6 |
| 31 | # define MAX_XLAT_TABLES 4 |
| 32 | #else |
| 33 | # define PLAT_ARM_MMAP_ENTRIES 10 |
| 34 | # define MAX_XLAT_TABLES 5 |
| 35 | #endif |
| 36 | |
| 37 | #if TRUSTED_BOARD_BOOT |
| 38 | # define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000 |
| 39 | #else |
| 40 | # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 |
| 41 | #endif |
| 42 | |
| 43 | #if TRUSTED_BOARD_BOOT |
| 44 | # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 |
| 45 | #else |
| 46 | # define PLAT_ARM_MAX_BL2_SIZE 0xC000 |
| 47 | #endif |
| 48 | |
| 49 | #endif /* ARM_BOARD_OPTIMISE_MEM */ |
| 50 | |
| 51 | #define PLAT_ARM_NSTIMER_FRAME_ID 0 |
| 52 | |
| 53 | #define PLAT_CSS_MHU_BASE 0x45000000 |
| 54 | |
| 55 | #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 |
| 56 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ |
| 57 | |
Chris Kay | 42fbdfc | 2018-05-10 14:27:45 +0100 | [diff] [blame] | 58 | #define PLAT_ARM_NSRAM_BASE 0x06000000 |
| 59 | #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ |
| 60 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 61 | #define PLAT_MAX_PWR_LVL U(1) |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 62 | |
| 63 | #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ |
| 64 | CSS_IRQ_MHU |
| 65 | |
| 66 | #define PLAT_ARM_G0_IRQS ARM_G0_IRQS |
| 67 | |
| 68 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) |
| 69 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 70 | |
| 71 | #define CSS_SGI_DEVICE_BASE (0x20000000) |
| 72 | #define CSS_SGI_DEVICE_SIZE (0x20000000) |
| 73 | #define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \ |
| 74 | CSS_SGI_DEVICE_BASE, \ |
| 75 | CSS_SGI_DEVICE_SIZE, \ |
| 76 | MT_DEVICE | MT_RW | MT_SECURE) |
| 77 | |
| 78 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 |
| 79 | #define SGI_BOOT_CFG_ADDR 0x45410000 |
| 80 | #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 |
| 81 | #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 6 |
| 82 | |
| 83 | /* GIC related constants */ |
| 84 | #define PLAT_ARM_GICD_BASE 0x30000000 |
| 85 | #define PLAT_ARM_GICC_BASE 0x2C000000 |
| 86 | #define PLAT_ARM_GICR_BASE 0x300C0000 |
| 87 | |
| 88 | /* Platform ID address */ |
| 89 | #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) |
| 90 | #ifndef __ASSEMBLY__ |
| 91 | /* SSC_VERSION related accessors */ |
| 92 | /* Returns the part number of the platform */ |
| 93 | #define GET_SGI_PART_NUM \ |
| 94 | GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION)) |
| 95 | /* Returns the configuration number of the platform */ |
| 96 | #define GET_SGI_CONFIG_NUM \ |
| 97 | GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) |
| 98 | #endif /* __ASSEMBLY__ */ |
| 99 | |
Roberto Vargas | bcca6c6 | 2018-06-11 16:15:35 +0100 | [diff] [blame] | 100 | /******************************************************************************* |
| 101 | * Memprotect definitions |
| 102 | ******************************************************************************/ |
| 103 | /* PSCI memory protect definitions: |
| 104 | * This variable is stored in a non-secure flash because some ARM reference |
| 105 | * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT |
| 106 | * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. |
| 107 | */ |
| 108 | #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ |
| 109 | V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 110 | |
| 111 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 112 | #endif /* PLATFORM_DEF_H */ |