johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 1 | /* |
Bipin Ravi | 9cafab8 | 2023-12-20 14:32:02 -0600 | [diff] [blame] | 2 | * Copyright (c) 2021-2024, Arm Limited. All rights reserved. |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 10 | #include <cortex_x3.h> |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 17 | #error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 18 | #endif |
| 19 | |
| 20 | /* 64-bit only core */ |
| 21 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 22 | #error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 23 | #endif |
| 24 | |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 25 | #if WORKAROUND_CVE_2022_23960 |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 26 | wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 27 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 28 | |
Sona Mathew | 35c7d39 | 2023-10-03 17:09:09 -0500 | [diff] [blame] | 29 | workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 |
| 30 | sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ |
| 31 | CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH |
| 32 | workaround_reset_end cortex_x3, ERRATUM(2070301) |
| 33 | |
| 34 | check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) |
| 35 | |
Bipin Ravi | dfa4cf4 | 2023-12-20 14:53:37 -0600 | [diff] [blame] | 36 | workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875 |
| 37 | sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22) |
| 38 | workaround_reset_end cortex_x3, ERRATUM(2266875) |
| 39 | |
| 40 | check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0) |
| 41 | |
Bipin Ravi | 9cafab8 | 2023-12-20 14:32:02 -0600 | [diff] [blame] | 42 | workaround_runtime_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506 |
| 43 | sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0) |
| 44 | workaround_runtime_end cortex_x3, ERRATUM(2302506), NO_ISB |
| 45 | |
| 46 | check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1) |
| 47 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 48 | workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 |
Sona Mathew | 45c1524 | 2023-06-20 00:16:44 -0500 | [diff] [blame] | 49 | sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 50 | workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB |
Boyan Karatotev | 6559dbd | 2022-10-03 14:18:28 +0100 | [diff] [blame] | 51 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 52 | check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) |
Harrison Mutai | 82dd5ac | 2022-11-11 14:09:55 +0000 | [diff] [blame] | 53 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 54 | workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 |
Harrison Mutai | 82dd5ac | 2022-11-11 14:09:55 +0000 | [diff] [blame] | 55 | /* Disable retention control for WFI and WFE. */ |
| 56 | mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 |
| 57 | bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 |
| 58 | bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 |
| 59 | msr CORTEX_X3_CPUPWRCTLR_EL1, x0 |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 60 | workaround_reset_end cortex_x3, ERRATUM(2615812) |
Harrison Mutai | 82dd5ac | 2022-11-11 14:09:55 +0000 | [diff] [blame] | 61 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 62 | check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) |
Harrison Mutai | 82dd5ac | 2022-11-11 14:09:55 +0000 | [diff] [blame] | 63 | |
Bipin Ravi | 42c6eb5 | 2024-01-25 15:38:46 -0600 | [diff] [blame] | 64 | workaround_runtime_start cortex_x3, ERRATUM(2641945), ERRATA_X3_2641945 |
| 65 | sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) |
| 66 | workaround_runtime_end cortex_x3, ERRATUM(2641945), NO_ISB |
| 67 | |
| 68 | check_erratum_ls cortex_x3, ERRATUM(2641945), CPU_REV(1, 0) |
| 69 | |
Sona Mathew | 9516858 | 2023-09-05 14:10:03 -0500 | [diff] [blame] | 70 | workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 |
| 71 | /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ |
| 72 | sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 |
| 73 | sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 |
| 74 | workaround_reset_end cortex_x3, ERRATUM(2742421) |
| 75 | |
| 76 | check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) |
| 77 | |
Harrison Mutai | 5177554 | 2023-12-12 11:17:19 +0000 | [diff] [blame] | 78 | workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088 |
| 79 | /* dsb before isb of power down sequence */ |
| 80 | dsb sy |
| 81 | workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB |
| 82 | |
| 83 | check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1) |
| 84 | |
Sona Mathew | 2eab9d0 | 2023-11-06 13:48:22 -0600 | [diff] [blame] | 85 | workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509 |
| 86 | /* Set CPUACTLR3_EL1 bit 47 */ |
| 87 | sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47 |
| 88 | workaround_reset_end cortex_x3, ERRATUM(2779509) |
| 89 | |
| 90 | check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1) |
| 91 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 92 | workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 93 | #if IMAGE_BL31 |
Sona Mathew | 45c1524 | 2023-06-20 00:16:44 -0500 | [diff] [blame] | 94 | override_vector_table wa_cve_vbar_cortex_x3 |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 95 | #endif /* IMAGE_BL31 */ |
| 96 | workaround_reset_end cortex_x3, CVE(2022, 23960) |
| 97 | |
| 98 | check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
Sona Mathew | ed5e976 | 2023-06-19 21:30:45 -0500 | [diff] [blame] | 99 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 100 | cpu_reset_func_start cortex_x3 |
Sona Mathew | ed5e976 | 2023-06-19 21:30:45 -0500 | [diff] [blame] | 101 | /* Disable speculative loads */ |
| 102 | msr SSBS, xzr |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 103 | cpu_reset_func_end cortex_x3 |
Sona Mathew | ed5e976 | 2023-06-19 21:30:45 -0500 | [diff] [blame] | 104 | |
| 105 | /* ---------------------------------------------------- |
| 106 | * HW will do the cache maintenance while powering down |
| 107 | * ---------------------------------------------------- |
| 108 | */ |
| 109 | func cortex_x3_core_pwr_dwn |
Harrison Mutai | 5177554 | 2023-12-12 11:17:19 +0000 | [diff] [blame] | 110 | apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 |
Sona Mathew | ed5e976 | 2023-06-19 21:30:45 -0500 | [diff] [blame] | 111 | /* --------------------------------------------------- |
| 112 | * Enable CPU power down bit in power control register |
| 113 | * --------------------------------------------------- |
| 114 | */ |
Sona Mathew | 45c1524 | 2023-06-20 00:16:44 -0500 | [diff] [blame] | 115 | sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
Harrison Mutai | 5177554 | 2023-12-12 11:17:19 +0000 | [diff] [blame] | 116 | apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088 |
Sona Mathew | ed5e976 | 2023-06-19 21:30:45 -0500 | [diff] [blame] | 117 | isb |
| 118 | ret |
| 119 | endfunc cortex_x3_core_pwr_dwn |
| 120 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 121 | errata_report_shim cortex_x3 |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 122 | |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 123 | /* --------------------------------------------- |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 124 | * This function provides Cortex-X3- |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 125 | * specific register information for crash |
| 126 | * reporting. It needs to return with x6 |
| 127 | * pointing to a list of register names in ascii |
| 128 | * and x8 - x15 having values of registers to be |
| 129 | * reported. |
| 130 | * --------------------------------------------- |
| 131 | */ |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 132 | .section .rodata.cortex_x3_regs, "aS" |
| 133 | cortex_x3_regs: /* The ascii list of register names to be reported */ |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 134 | .asciz "cpuectlr_el1", "" |
| 135 | |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 136 | func cortex_x3_cpu_reg_dump |
| 137 | adr x6, cortex_x3_regs |
| 138 | mrs x8, CORTEX_X3_CPUECTLR_EL1 |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 139 | ret |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 140 | endfunc cortex_x3_cpu_reg_dump |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 141 | |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 142 | declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \ |
| 143 | cortex_x3_reset_func, \ |
| 144 | cortex_x3_core_pwr_dwn |