| developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PLAT_DEF_H__ |
| 32 | #define __PLAT_DEF_H__ |
| 33 | |
| 34 | #define MT8173_PRIMARY_CPU 0x0 |
| 35 | |
| 36 | /* Special value used to verify platform parameters from BL2 to BL3-1 */ |
| 37 | #define MT_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL |
| 38 | |
| 39 | #define IO_PHYS (0x10000000) |
| 40 | #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) |
| 41 | #define GPIO_BASE (IO_PHYS + 0x5000) |
| 42 | #define SPM_BASE (IO_PHYS + 0x6000) |
| 43 | #define RGU_BASE (IO_PHYS + 0x7000) |
| 44 | #define PMIC_WRAP_BASE (IO_PHYS + 0xD000) |
| 45 | #define MCUCFG_BASE (IO_PHYS + 0x200000) |
| 46 | #define TRNG_base (IO_PHYS + 0x20F000) |
| 47 | #define MT_GIC_BASE (IO_PHYS + 0x220000) |
| 48 | #define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000) |
| 49 | |
| 50 | /* Aggregate of all devices in the first GB */ |
| 51 | #define MTK_DEV_RNG0_BASE IO_PHYS |
| 52 | #define MTK_DEV_RNG0_SIZE 0x400000 |
| 53 | #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) |
| 54 | #define MTK_DEV_RNG1_SIZE 0x4000000 |
| 55 | |
| 56 | /******************************************************************************* |
| 57 | * UART related constants |
| 58 | ******************************************************************************/ |
| 59 | #define MT8173_UART0_BASE (IO_PHYS + 0x01002000) |
| 60 | #define MT8173_UART1_BASE (IO_PHYS + 0x01003000) |
| 61 | #define MT8173_UART2_BASE (IO_PHYS + 0x01004000) |
| 62 | #define MT8173_UART3_BASE (IO_PHYS + 0x01005000) |
| 63 | |
| 64 | #define MT8173_BAUDRATE (115200) |
| 65 | #define MT8173_UART_CLOCK (26000000) |
| 66 | |
| 67 | /******************************************************************************* |
| 68 | * System counter frequency related constants |
| 69 | ******************************************************************************/ |
| 70 | #define SYS_COUNTER_FREQ_IN_TICKS 13000000 |
| 71 | #define SYS_COUNTER_FREQ_IN_MHZ 13 |
| 72 | |
| 73 | /******************************************************************************* |
| 74 | * GIC-400 & interrupt handling related constants |
| 75 | ******************************************************************************/ |
| 76 | |
| 77 | /* Base MTK_platform compatible GIC memory map */ |
| 78 | #define BASE_GICD_BASE (MT_GIC_BASE + 0x1000) |
| 79 | #define BASE_GICC_BASE (MT_GIC_BASE + 0x2000) |
| 80 | #define BASE_GICR_BASE 0 /* no GICR in GIC-400 */ |
| 81 | #define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) |
| 82 | #define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) |
| 83 | #define INT_POL_CTL0 0x10200620 |
| 84 | |
| 85 | #define GIC_PRIVATE_SIGNALS (32) |
| 86 | |
| 87 | /******************************************************************************* |
| 88 | * CCI-400 related constants |
| 89 | ******************************************************************************/ |
| 90 | #define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 91 | #define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 |
| 92 | |
| 93 | /******************************************************************************* |
| 94 | * WDT related constants |
| 95 | ******************************************************************************/ |
| 96 | #define MTK_WDT_BASE (RGU_BASE + 0) |
| 97 | #define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014) |
| 98 | |
| 99 | #define MTK_WDT_MODE_DUAL_MODE 0x0040 |
| 100 | #define MTK_WDT_MODE_IRQ 0x0008 |
| 101 | #define MTK_WDT_MODE_KEY 0x22000000 |
| 102 | #define MTK_WDT_MODE_EXTEN 0x0004 |
| 103 | #define MTK_WDT_SWRST_KEY 0x1209 |
| 104 | |
| 105 | /* FIQ platform related define */ |
| 106 | #define MT_IRQ_SEC_SGI_0 8 |
| 107 | #define MT_IRQ_SEC_SGI_1 9 |
| 108 | #define MT_IRQ_SEC_SGI_2 10 |
| 109 | #define MT_IRQ_SEC_SGI_3 11 |
| 110 | #define MT_IRQ_SEC_SGI_4 12 |
| 111 | #define MT_IRQ_SEC_SGI_5 13 |
| 112 | #define MT_IRQ_SEC_SGI_6 14 |
| 113 | #define MT_IRQ_SEC_SGI_7 15 |
| 114 | |
| 115 | #endif /* __PLAT_DEF_H__ */ |