Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 30 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 31 | #include <asm_macros.S> |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 32 | #include <bl_common.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 33 | #include <cortex_a53.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 34 | #include <cpu_macros.S> |
| 35 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 36 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 37 | /* --------------------------------------------- |
| 38 | * Disable L1 data cache and unified L2 cache |
| 39 | * --------------------------------------------- |
| 40 | */ |
| 41 | func cortex_a53_disable_dcache |
| 42 | mrs x1, sctlr_el3 |
| 43 | bic x1, x1, #SCTLR_C_BIT |
| 44 | msr sctlr_el3, x1 |
| 45 | isb |
| 46 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 47 | endfunc cortex_a53_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 48 | |
| 49 | /* --------------------------------------------- |
| 50 | * Disable intra-cluster coherency |
| 51 | * --------------------------------------------- |
| 52 | */ |
| 53 | func cortex_a53_disable_smp |
| 54 | mrs x0, CPUECTLR_EL1 |
| 55 | bic x0, x0, #CPUECTLR_SMP_BIT |
| 56 | msr CPUECTLR_EL1, x0 |
| 57 | isb |
| 58 | dsb sy |
| 59 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 60 | endfunc cortex_a53_disable_smp |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 61 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 62 | /* -------------------------------------------------- |
| 63 | * Errata Workaround for Cortex A53 Errata #826319. |
| 64 | * This applies only to revision <= r0p2 of Cortex A53. |
| 65 | * Inputs: |
| 66 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 67 | * Clobbers : x0 - x5 |
| 68 | * -------------------------------------------------- |
| 69 | */ |
| 70 | func errata_a53_826319_wa |
| 71 | /* |
| 72 | * Compare x0 against revision r0p2 |
| 73 | */ |
| 74 | cmp x0, #2 |
| 75 | b.ls apply_826319 |
| 76 | #if DEBUG |
| 77 | b print_revision_warning |
| 78 | #else |
| 79 | ret |
| 80 | #endif |
| 81 | apply_826319: |
| 82 | mrs x1, L2ACTLR_EL1 |
| 83 | bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN |
| 84 | orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH |
| 85 | msr L2ACTLR_EL1, x1 |
| 86 | ret |
| 87 | endfunc errata_a53_826319_wa |
| 88 | |
| 89 | /* -------------------------------------------------- |
| 90 | * Errata Workaround for Cortex A53 Errata #836870. |
| 91 | * This applies only to revision <= r0p3 of Cortex A53. |
| 92 | * From r0p4 and onwards, this errata is enabled by |
| 93 | * default. |
| 94 | * Inputs: |
| 95 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 96 | * Clobbers : x0 - x5 |
| 97 | * -------------------------------------------------- |
| 98 | */ |
| 99 | func errata_a53_836870_wa |
| 100 | /* |
| 101 | * Compare x0 against revision r0p3 |
| 102 | */ |
| 103 | cmp x0, #3 |
| 104 | b.ls apply_836870 |
| 105 | #if DEBUG |
| 106 | b print_revision_warning |
| 107 | #else |
| 108 | ret |
| 109 | #endif |
| 110 | apply_836870: |
| 111 | mrs x1, CPUACTLR_EL1 |
| 112 | orr x1, x1, #CPUACTLR_DTAH |
| 113 | msr CPUACTLR_EL1, x1 |
| 114 | ret |
| 115 | endfunc errata_a53_836870_wa |
| 116 | |
| 117 | /* ------------------------------------------------- |
| 118 | * The CPU Ops reset function for Cortex-A53. |
| 119 | * Clobbers: x0-x5, x15, x19, x30 |
| 120 | * ------------------------------------------------- |
| 121 | */ |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 122 | func cortex_a53_reset_func |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 123 | mov x19, x30 |
| 124 | mrs x0, midr_el1 |
| 125 | |
| 126 | /* |
| 127 | * Extract the variant[20:23] and revision[0:3] from x0 |
| 128 | * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. |
| 129 | * First extract x0[16:23] to x15[0:7] and zero fill the rest. |
| 130 | * Then extract x0[0:3] into x15[0:3] retaining other bits. |
| 131 | */ |
| 132 | ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), \ |
| 133 | #(MIDR_REV_BITS + MIDR_VAR_BITS) |
| 134 | bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS |
| 135 | |
| 136 | #if ERRATA_A53_826319 |
| 137 | mov x0, x15 |
| 138 | bl errata_a53_826319_wa |
| 139 | #endif |
| 140 | |
| 141 | #if ERRATA_A53_836870 |
| 142 | mov x0, x15 |
| 143 | bl errata_a53_836870_wa |
| 144 | #endif |
| 145 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 146 | /* --------------------------------------------- |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 147 | * As a bare minimum enable the SMP bit if it is |
| 148 | * not already set. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 149 | * --------------------------------------------- |
| 150 | */ |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 151 | mrs x0, CPUECTLR_EL1 |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 152 | tst x0, #CPUECTLR_SMP_BIT |
| 153 | b.ne skip_smp_setup |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 154 | orr x0, x0, #CPUECTLR_SMP_BIT |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 155 | msr CPUECTLR_EL1, x0 |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 156 | skip_smp_setup: |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 157 | isb |
| 158 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 159 | endfunc cortex_a53_reset_func |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 160 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 161 | func cortex_a53_core_pwr_dwn |
| 162 | mov x18, x30 |
| 163 | |
| 164 | /* --------------------------------------------- |
| 165 | * Turn off caches. |
| 166 | * --------------------------------------------- |
| 167 | */ |
| 168 | bl cortex_a53_disable_dcache |
| 169 | |
| 170 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 171 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 172 | * --------------------------------------------- |
| 173 | */ |
| 174 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 175 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 176 | |
| 177 | /* --------------------------------------------- |
| 178 | * Come out of intra cluster coherency |
| 179 | * --------------------------------------------- |
| 180 | */ |
| 181 | mov x30, x18 |
| 182 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 183 | endfunc cortex_a53_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 184 | |
| 185 | func cortex_a53_cluster_pwr_dwn |
| 186 | mov x18, x30 |
| 187 | |
| 188 | /* --------------------------------------------- |
| 189 | * Turn off caches. |
| 190 | * --------------------------------------------- |
| 191 | */ |
| 192 | bl cortex_a53_disable_dcache |
| 193 | |
| 194 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 195 | * Flush L1 caches. |
| 196 | * --------------------------------------------- |
| 197 | */ |
| 198 | mov x0, #DCCISW |
| 199 | bl dcsw_op_level1 |
| 200 | |
| 201 | /* --------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 202 | * Disable the optional ACP. |
| 203 | * --------------------------------------------- |
| 204 | */ |
| 205 | bl plat_disable_acp |
| 206 | |
| 207 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 208 | * Flush L2 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 209 | * --------------------------------------------- |
| 210 | */ |
| 211 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 212 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 213 | |
| 214 | /* --------------------------------------------- |
| 215 | * Come out of intra cluster coherency |
| 216 | * --------------------------------------------- |
| 217 | */ |
| 218 | mov x30, x18 |
| 219 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 220 | endfunc cortex_a53_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 221 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 222 | /* --------------------------------------------- |
| 223 | * This function provides cortex_a53 specific |
| 224 | * register information for crash reporting. |
| 225 | * It needs to return with x6 pointing to |
| 226 | * a list of register names in ascii and |
| 227 | * x8 - x15 having values of registers to be |
| 228 | * reported. |
| 229 | * --------------------------------------------- |
| 230 | */ |
| 231 | .section .rodata.cortex_a53_regs, "aS" |
| 232 | cortex_a53_regs: /* The ascii list of register names to be reported */ |
| 233 | .asciz "cpuectlr_el1", "" |
| 234 | |
| 235 | func cortex_a53_cpu_reg_dump |
| 236 | adr x6, cortex_a53_regs |
| 237 | mrs x8, CPUECTLR_EL1 |
| 238 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 239 | endfunc cortex_a53_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 240 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 241 | declare_cpu_ops cortex_a53, CORTEX_A53_MIDR |