Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * Copyright (c) 2019, Intel Corporation. All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #include <arch.h> |
| 9 | #include <arch_helpers.h> |
| 10 | #include <common/bl_common.h> |
| 11 | #include <common/debug.h> |
| 12 | #include <common/desc_image_load.h> |
| 13 | #include <drivers/generic_delay_timer.h> |
| 14 | #include <drivers/synopsys/dw_mmc.h> |
| 15 | #include <drivers/ti/uart/uart_16550.h> |
| 16 | #include <lib/xlat_tables/xlat_tables.h> |
| 17 | #include <platform_def.h> |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 18 | |
| 19 | #include "agilex_clock_manager.h" |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 20 | #include "agilex_memory_controller.h" |
| 21 | #include "agilex_pinmux.h" |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 22 | #include "agilex_reset_manager.h" |
| 23 | #include "agilex_system_manager.h" |
| 24 | |
| 25 | #include "ccu/ncore_ccu.h" |
| 26 | #include "qspi/cadence_qspi.h" |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 27 | #include "socfpga_handoff.h" |
Hadi Asyrafi | 6f8a2b2 | 2019-10-23 18:34:14 +0800 | [diff] [blame] | 28 | #include "socfpga_mailbox.h" |
Hadi Asyrafi | f0fa807 | 2019-10-23 17:02:55 +0800 | [diff] [blame] | 29 | #include "socfpga_private.h" |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 30 | #include "wdt/watchdog.h" |
| 31 | |
| 32 | |
| 33 | const mmap_region_t agilex_plat_mmap[] = { |
| 34 | MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, |
| 35 | MT_MEMORY | MT_RW | MT_NS), |
| 36 | MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, |
| 37 | MT_DEVICE | MT_RW | MT_NS), |
| 38 | MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, |
| 39 | MT_DEVICE | MT_RW | MT_SECURE), |
| 40 | MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, |
| 41 | MT_NON_CACHEABLE | MT_RW | MT_SECURE), |
| 42 | MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, |
| 43 | MT_DEVICE | MT_RW | MT_SECURE), |
| 44 | MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, |
| 45 | MT_DEVICE | MT_RW | MT_NS), |
| 46 | MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, |
| 47 | MT_DEVICE | MT_RW | MT_NS), |
| 48 | {0}, |
| 49 | }; |
| 50 | |
| 51 | boot_source_type boot_source; |
| 52 | |
| 53 | void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, |
| 54 | u_register_t x2, u_register_t x4) |
| 55 | { |
| 56 | static console_16550_t console; |
| 57 | handoff reverse_handoff_ptr; |
| 58 | |
| 59 | generic_delay_timer_init(); |
| 60 | |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 61 | if (socfpga_get_handoff(&reverse_handoff_ptr)) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 62 | return; |
| 63 | config_pinmux(&reverse_handoff_ptr); |
| 64 | boot_source = reverse_handoff_ptr.boot_source; |
| 65 | config_clkmgr_handoff(&reverse_handoff_ptr); |
| 66 | |
| 67 | enable_nonsecure_access(); |
| 68 | deassert_peripheral_reset(); |
| 69 | config_hps_hs_before_warm_reset(); |
| 70 | |
Hadi Asyrafi | a813fed | 2019-08-14 13:49:00 +0800 | [diff] [blame] | 71 | watchdog_init(get_wdt_clk()); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 72 | |
Hadi Asyrafi | a813fed | 2019-08-14 13:49:00 +0800 | [diff] [blame] | 73 | console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 74 | &console); |
| 75 | |
| 76 | socfpga_delay_timer_init(); |
| 77 | init_ncore_ccu(); |
| 78 | init_hard_memory_controller(); |
| 79 | enable_ns_bridge_access(); |
| 80 | } |
| 81 | |
| 82 | |
| 83 | void bl2_el3_plat_arch_setup(void) |
| 84 | { |
| 85 | |
| 86 | struct mmc_device_info info; |
| 87 | const mmap_region_t bl_regions[] = { |
| 88 | MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, |
| 89 | MT_MEMORY | MT_RW | MT_SECURE), |
| 90 | MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, |
| 91 | MT_CODE | MT_SECURE), |
| 92 | MAP_REGION_FLAT(BL_RO_DATA_BASE, |
| 93 | BL_RO_DATA_END - BL_RO_DATA_BASE, |
| 94 | MT_RO_DATA | MT_SECURE), |
| 95 | #if USE_COHERENT_MEM_BAR |
| 96 | MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, |
| 97 | BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, |
| 98 | MT_DEVICE | MT_RW | MT_SECURE), |
| 99 | #endif |
| 100 | {0}, |
| 101 | }; |
| 102 | |
| 103 | setup_page_tables(bl_regions, agilex_plat_mmap); |
| 104 | |
| 105 | enable_mmu_el3(0); |
| 106 | |
Hadi Asyrafi | a813fed | 2019-08-14 13:49:00 +0800 | [diff] [blame] | 107 | dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 108 | |
| 109 | info.mmc_dev_type = MMC_IS_SD; |
| 110 | info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; |
| 111 | |
| 112 | mailbox_init(); |
| 113 | |
| 114 | switch (boot_source) { |
| 115 | case BOOT_SOURCE_SDMMC: |
| 116 | dw_mmc_init(¶ms, &info); |
| 117 | socfpga_io_setup(boot_source); |
| 118 | break; |
| 119 | |
| 120 | case BOOT_SOURCE_QSPI: |
| 121 | mailbox_set_qspi_open(); |
| 122 | mailbox_set_qspi_direct(); |
| 123 | cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, |
| 124 | QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, |
| 125 | QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); |
| 126 | socfpga_io_setup(boot_source); |
| 127 | break; |
| 128 | |
| 129 | default: |
| 130 | ERROR("Unsupported boot source\n"); |
| 131 | panic(); |
| 132 | break; |
| 133 | } |
| 134 | } |
| 135 | |
| 136 | uint32_t get_spsr_for_bl33_entry(void) |
| 137 | { |
| 138 | unsigned long el_status; |
| 139 | unsigned int mode; |
| 140 | uint32_t spsr; |
| 141 | |
| 142 | /* Figure out what mode we enter the non-secure world in */ |
| 143 | el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; |
| 144 | el_status &= ID_AA64PFR0_ELX_MASK; |
| 145 | |
| 146 | mode = (el_status) ? MODE_EL2 : MODE_EL1; |
| 147 | |
| 148 | /* |
| 149 | * TODO: Consider the possibility of specifying the SPSR in |
| 150 | * the FIP ToC and allowing the platform to have a say as |
| 151 | * well. |
| 152 | */ |
| 153 | spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
| 154 | return spsr; |
| 155 | } |
| 156 | |
| 157 | |
| 158 | int bl2_plat_handle_post_image_load(unsigned int image_id) |
| 159 | { |
| 160 | bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); |
| 161 | |
| 162 | switch (image_id) { |
| 163 | case BL33_IMAGE_ID: |
| 164 | bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); |
| 165 | bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); |
| 166 | break; |
| 167 | default: |
| 168 | break; |
| 169 | } |
| 170 | |
| 171 | return 0; |
| 172 | } |
| 173 | |
| 174 | /******************************************************************************* |
| 175 | * Perform any BL3-1 platform setup code |
| 176 | ******************************************************************************/ |
| 177 | void bl2_platform_setup(void) |
| 178 | { |
| 179 | } |
| 180 | |