| Jacky Bai | 4d93d1d | 2020-07-02 14:39:58 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2021-2024 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 13 | #define PLATFORM_LINKER_ARCH aarch64 |
| 14 | |
| 15 | #define PLATFORM_STACK_SIZE 0x400 |
| 16 | #define CACHE_WRITEBACK_GRANULE 64 |
| 17 | |
| 18 | #define PLAT_PRIMARY_CPU 0x0 |
| 19 | #define PLATFORM_MAX_CPU_PER_CLUSTER 2 |
| 20 | #define PLATFORM_CLUSTER_COUNT 1 |
| 21 | #define PLATFORM_CORE_COUNT 2 |
| 22 | #define PLATFORM_CLUSTER0_CORE_COUNT 2 |
| 23 | #define PLATFORM_CLUSTER1_CORE_COUNT 0 |
| 24 | |
| 25 | #define IMX_PWR_LVL0 MPIDR_AFFLVL0 |
| 26 | #define IMX_PWR_LVL1 MPIDR_AFFLVL1 |
| 27 | #define IMX_PWR_LVL2 MPIDR_AFFLVL2 |
| 28 | |
| 29 | #define PWR_DOMAIN_AT_MAX_LVL U(1) |
| 30 | #define PLAT_MAX_PWR_LVL U(2) |
| 31 | #define PLAT_MAX_OFF_STATE U(4) |
| 32 | #define PLAT_MAX_RET_STATE U(2) |
| 33 | |
| 34 | #define PLAT_WAIT_RET_STATE U(1) |
| 35 | #define PLAT_STOP_OFF_STATE U(3) |
| 36 | |
| 37 | #define BL31_BASE 0x20040000 |
| 38 | #define BL31_LIMIT 0x20070000 |
| 39 | |
| 40 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) |
| 41 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) |
| 42 | |
| 43 | #define MAX_XLAT_TABLES 8 |
| 44 | #define MAX_MMAP_REGIONS 9 |
| 45 | |
| 46 | #define PLAT_GICD_BASE U(0x2d400000) |
| 47 | #define PLAT_GICR_BASE U(0x2d440000) |
| 48 | #define DEVICE0_BASE U(0x20000000) |
| 49 | #define DEVICE0_SIZE U(0x10000000) |
| 50 | #define DEVICE1_BASE U(0x30000000) |
| 51 | #define DEVICE1_SIZE U(0x10000000) |
| 52 | #define IMX_LPUART4_BASE U(0x29390000) |
| 53 | #define IMX_LPUART5_BASE U(0x293a0000) |
| 54 | #define IMX_LPUART_BASE IMX_LPUART5_BASE |
| 55 | #define IMX_BOOT_UART_CLK_IN_HZ 24000000 |
| 56 | #define IMX_CONSOLE_BAUDRATE 115200 |
| 57 | |
| 58 | #define IMX_CGC1_BASE U(0x292c0000) |
| 59 | #define IMX_PCC3_BASE U(0x292d0000) |
| 60 | #define IMX_PCC4_BASE U(0x29800000) |
| 61 | #define IMX_SIM2_BASE U(0x2da50000) |
| 62 | #define IMX_CGC2_BASE U(0x2da60000) |
| 63 | #define IMX_PCC5_BASE U(0x2da70000) |
| 64 | #define IMX_CMC1_BASE U(0x29240000) |
| 65 | #define IMX_SIM1_BASE U(0x29290000) |
| 66 | #define IMX_WDOG3_BASE U(0x292a0000) |
| 67 | #define IMX_GPIOE_BASE U(0x2D000000) |
| 68 | #define IMX_GPIOD_BASE U(0x2E200000) |
| 69 | #define IMX_GPIOF_BASE U(0x2D010000) |
| 70 | |
| 71 | #define SRAM0_BASE U(0x2201F000) |
| 72 | |
| 73 | #define IMX_ROM_ENTRY U(0x1000) |
| 74 | #define COUNTER_FREQUENCY 1000000 |
| 75 | |
| 76 | #define PLAT_NS_IMAGE_OFFSET 0x80200000 |
| 77 | |
| 78 | #define BL31_NOBITS_BASE 0x20058000 |
| 79 | #define BL31_NOBITS_LIMIT 0x2006d000 |
| 80 | |
| 81 | #define BL31_RWDATA_BASE 0x2006d000 |
| 82 | #define BL31_RWDATA_LIMIT 0x20070000 |
| 83 | |
| 84 | /* system memory map define */ |
| 85 | #define DEVICE0_MAP MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW) |
| 86 | #define DEVICE1_MAP MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW) |
| 87 | /* MU and FSB */ |
| 88 | #define ELE_MAP MAP_REGION_FLAT(0x27010000, 0x20000, MT_DEVICE | MT_RW | MT_NS) |
| 89 | #define SEC_SIM_MAP MAP_REGION_FLAT(0x2802B000, 0x1000, MT_DEVICE | MT_RW | MT_NS) /* SEC SIM */ |
| 90 | /* For SCMI shared memory region */ |
| 91 | #define SRAM0_MAP MAP_REGION_FLAT(SRAM0_BASE, 0x1000, MT_RW | MT_DEVICE) |
| 92 | |
| 93 | #endif /* PLATFORM_DEF_H */ |