| Jiafei Pan | 46367ad | 2018-03-02 07:23:30 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef _SOC_TZASC_H_ |
| 8 | #define _SOC_TZASC_H_ |
| 9 | |
| 10 | #include "tzc380.h" |
| 11 | |
| 12 | #define MAX_NUM_TZC_REGION 3 |
| 13 | |
| 14 | /* TZASC related constants */ |
| 15 | #define TZASC_CONFIGURATION_REG 0x000 |
| 16 | #define TZASC_SECURITY_INV_REG 0x034 |
| 17 | #define TZASC_SECURITY_INV_EN 0x1 |
| 18 | #define TZASC_REGIONS_REG 0x100 |
| 19 | /* As region address should address atleast 32KB memory. */ |
| 20 | #define TZASC_REGION_LOWADDR_MASK 0xFFFF8000 |
| 21 | #define TZASC_REGION_LOWADDR_OFFSET 0x0 |
| 22 | #define TZASC_REGION_HIGHADDR_OFFSET 0x4 |
| 23 | #define TZASC_REGION_ATTR_OFFSET 0x8 |
| 24 | #define TZASC_REGION_ENABLED 1 |
| 25 | #define TZASC_REGION_DISABLED 0 |
| 26 | #define TZASC_REGION_SIZE_32KB 0xE |
| 27 | #define TZASC_REGION_SIZE_64KB 0xF |
| 28 | #define TZASC_REGION_SIZE_128KB 0x10 |
| 29 | #define TZASC_REGION_SIZE_256KB 0x11 |
| 30 | #define TZASC_REGION_SIZE_512KB 0x12 |
| 31 | #define TZASC_REGION_SIZE_1MB 0x13 |
| 32 | #define TZASC_REGION_SIZE_2MB 0x14 |
| 33 | #define TZASC_REGION_SIZE_4MB 0x15 |
| 34 | #define TZASC_REGION_SIZE_8MB 0x16 |
| 35 | #define TZASC_REGION_SIZE_16MB 0x17 |
| 36 | #define TZASC_REGION_SIZE_32MB 0x18 |
| 37 | #define TZASC_REGION_SIZE_64MB 0x19 |
| 38 | #define TZASC_REGION_SIZE_128MB 0x1A |
| 39 | #define TZASC_REGION_SIZE_256MB 0x1B |
| 40 | #define TZASC_REGION_SIZE_512MB 0x1C |
| 41 | #define TZASC_REGION_SIZE_1GB 0x1D |
| 42 | #define TZASC_REGION_SIZE_2GB 0x1E |
| 43 | #define TZASC_REGION_SIZE_4GB 0x1F |
| 44 | #define TZASC_REGION_SIZE_8GB 0x20 |
| 45 | #define TZASC_REGION_SIZE_16GB 0x21 |
| 46 | #define TZASC_REGION_SIZE_32GB 0x22 |
| 47 | #define TZASC_REGION_SECURITY_SR (1 << 3) |
| 48 | #define TZASC_REGION_SECURITY_SW (1 << 2) |
| 49 | #define TZASC_REGION_SECURITY_SRW (TZASC_REGION_SECURITY_SR| \ |
| 50 | TZASC_REGION_SECURITY_SW) |
| 51 | #define TZASC_REGION_SECURITY_NSR (1 << 1) |
| 52 | #define TZASC_REGION_SECURITY_NSW 1 |
| 53 | #define TZASC_REGION_SECURITY_NSRW (TZASC_REGION_SECURITY_NSR| \ |
| 54 | TZASC_REGION_SECURITY_NSW) |
| 55 | |
| 56 | #define CSU_SEC_ACCESS_REG_OFFSET 0x21C |
| 57 | #define TZASC_BYPASS_MUX_DISABLE 0x4 |
| 58 | #define CCI_TERMINATE_BARRIER_TX 0x8 |
| 59 | #define CONFIG_SYS_FSL_TZASC_ADDR 0x1500000 |
| 60 | |
| 61 | /* List of MAX_NUM_TZC_REGION TZC regions' boundaries and configurations. */ |
| 62 | |
| 63 | static const struct tzc380_reg tzc380_reg_list[] = { |
| 64 | { |
| 65 | TZASC_REGION_SECURITY_NSRW, /* .secure attr */ |
| 66 | 0x0, /* .enabled */ |
| 67 | 0x0, /* .lowaddr */ |
| 68 | 0x0, /* .highaddr */ |
| 69 | 0x0, /* .size */ |
| 70 | 0x0, /* .submask */ |
| 71 | }, |
| 72 | { |
| 73 | TZASC_REGION_SECURITY_SRW, |
| 74 | TZASC_REGION_ENABLED, |
| 75 | 0xFC000000, |
| 76 | 0x0, |
| 77 | TZASC_REGION_SIZE_64MB, |
| 78 | 0x80, /* Disable region 7 */ |
| 79 | }, |
| 80 | /* reserve 2M non-scure memory for OPTEE public memory */ |
| 81 | { |
| 82 | TZASC_REGION_SECURITY_SRW, |
| 83 | TZASC_REGION_ENABLED, |
| 84 | 0xFF800000, |
| 85 | 0x0, |
| 86 | TZASC_REGION_SIZE_8MB, |
| 87 | 0xC0, /* Disable region 6 & 7 */ |
| 88 | }, |
| 89 | |
| 90 | {} |
| 91 | }; |
| 92 | |
| 93 | #endif /* _SOC_TZASC_H_ */ |