blob: 2a1f2231deb1f2460a423934d452746fabc4d068 [file] [log] [blame]
Samuel Hollandb8566642017-08-12 04:07:39 -05001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <debug.h>
10#include <delay_timer.h>
Samuel Holland0a9018c2017-08-12 04:07:39 -050011#include <gicv2.h>
Samuel Hollandb8566642017-08-12 04:07:39 -050012#include <mmio.h>
13#include <platform.h>
14#include <platform_def.h>
15#include <psci.h>
16#include <sunxi_mmap.h>
Samuel Holland0a9018c2017-08-12 04:07:39 -050017#include <sunxi_cpucfg.h>
Samuel Hollandb8566642017-08-12 04:07:39 -050018
19#define SUNXI_WDOG0_CTRL_REG (SUNXI_WDOG_BASE + 0x0010)
20#define SUNXI_WDOG0_CFG_REG (SUNXI_WDOG_BASE + 0x0014)
21#define SUNXI_WDOG0_MODE_REG (SUNXI_WDOG_BASE + 0x0018)
22
Samuel Holland321c0ab2017-08-12 04:07:39 -050023#include "sunxi_private.h"
24
Samuel Holland0a9018c2017-08-12 04:07:39 -050025#define mpidr_is_valid(mpidr) ( \
26 MPIDR_AFFLVL3_VAL(mpidr) == 0 && \
27 MPIDR_AFFLVL2_VAL(mpidr) == 0 && \
28 MPIDR_AFFLVL1_VAL(mpidr) < PLATFORM_CLUSTER_COUNT && \
29 MPIDR_AFFLVL0_VAL(mpidr) < PLATFORM_MAX_CPUS_PER_CLUSTER)
30
31static int sunxi_pwr_domain_on(u_register_t mpidr)
32{
33 if (mpidr_is_valid(mpidr) == 0)
34 return PSCI_E_INTERN_FAIL;
35
36 sunxi_cpu_on(MPIDR_AFFLVL1_VAL(mpidr), MPIDR_AFFLVL0_VAL(mpidr));
37
38 return PSCI_E_SUCCESS;
39}
40
41static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
42{
43 gicv2_cpuif_disable();
44}
45
46static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
47{
48 gicv2_pcpu_distif_init();
49 gicv2_cpuif_enable();
50}
51
Samuel Hollandb8566642017-08-12 04:07:39 -050052static void __dead2 sunxi_system_off(void)
53{
Samuel Holland321c0ab2017-08-12 04:07:39 -050054 /* Turn off all secondary CPUs */
55 sunxi_disable_secondary_cpus(plat_my_core_pos());
56
Samuel Hollandb8566642017-08-12 04:07:39 -050057 ERROR("PSCI: Full shutdown not implemented, halting\n");
58 wfi();
59 panic();
60}
61
62static void __dead2 sunxi_system_reset(void)
63{
64 /* Reset the whole system when the watchdog times out */
65 mmio_write_32(SUNXI_WDOG0_CFG_REG, 1);
66 /* Enable the watchdog with the shortest timeout (0.5 seconds) */
67 mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1);
68 /* Wait for twice the watchdog timeout before panicking */
69 mdelay(1000);
70
71 ERROR("PSCI: System reset failed\n");
72 wfi();
73 panic();
74}
75
Samuel Holland0a9018c2017-08-12 04:07:39 -050076static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
77{
78 /* The non-secure entry point must be in DRAM */
Andre Przywara9f3cb8c2018-06-22 00:48:15 +010079 if (ns_entrypoint >= SUNXI_DRAM_BASE)
Samuel Holland0a9018c2017-08-12 04:07:39 -050080 return PSCI_E_SUCCESS;
81
82 return PSCI_E_INVALID_ADDRESS;
83}
84
Samuel Hollandb8566642017-08-12 04:07:39 -050085static plat_psci_ops_t sunxi_psci_ops = {
Samuel Holland0a9018c2017-08-12 04:07:39 -050086 .pwr_domain_on = sunxi_pwr_domain_on,
87 .pwr_domain_off = sunxi_pwr_domain_off,
88 .pwr_domain_on_finish = sunxi_pwr_domain_on_finish,
Samuel Hollandb8566642017-08-12 04:07:39 -050089 .system_off = sunxi_system_off,
90 .system_reset = sunxi_system_reset,
Samuel Holland0a9018c2017-08-12 04:07:39 -050091 .validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
Samuel Hollandb8566642017-08-12 04:07:39 -050092};
93
94int plat_setup_psci_ops(uintptr_t sec_entrypoint,
95 const plat_psci_ops_t **psci_ops)
96{
97 assert(psci_ops);
98
Samuel Holland0a9018c2017-08-12 04:07:39 -050099 for (int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) {
100 mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu),
101 sec_entrypoint & 0xffffffff);
102 mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu),
103 sec_entrypoint >> 32);
104 }
105
Samuel Hollandb8566642017-08-12 04:07:39 -0500106 *psci_ops = &sunxi_psci_ops;
107
108 return 0;
109}