blob: 8ecf49083b6ab1b879b8d952d4f20ab658db5c63 [file] [log] [blame]
Samuel Hollandb8566642017-08-12 04:07:39 -05001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <assert.h>
9#include <console.h>
10#include <debug.h>
11#include <generic_delay_timer.h>
12#include <gicv2.h>
13#include <platform.h>
14#include <platform_def.h>
15#include <sunxi_def.h>
16#include <sunxi_mmap.h>
17#include <uart_16550.h>
18
19#include "sunxi_private.h"
20
Amit Singh Tomar2f372242018-06-20 00:44:50 +053021static entry_point_info_t bl32_image_ep_info;
Samuel Hollandb8566642017-08-12 04:07:39 -050022static entry_point_info_t bl33_image_ep_info;
23
24static console_16550_t console;
25
26static const gicv2_driver_data_t sunxi_gic_data = {
27 .gicd_base = SUNXI_GICD_BASE,
28 .gicc_base = SUNXI_GICC_BASE,
29};
30
31void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
32 u_register_t arg2, u_register_t arg3)
33{
34 /* Initialize the debug console as soon as possible */
35 console_16550_register(SUNXI_UART0_BASE, SUNXI_UART0_CLK_IN_HZ,
36 SUNXI_UART0_BAUDRATE, &console);
37
Amit Singh Tomar2f372242018-06-20 00:44:50 +053038#ifdef BL32_BASE
39 /* Populate entry point information for BL32 */
40 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
41 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
42 bl32_image_ep_info.pc = BL32_BASE;
43#endif
44
Samuel Hollandb8566642017-08-12 04:07:39 -050045 /* Populate entry point information for BL33 */
46 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
47 /*
48 * Tell BL31 where the non-trusted software image
49 * is located and the entry state information
50 */
51 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
52 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
53 DISABLE_ALL_EXCEPTIONS);
54 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
Samuel Holland321c0ab2017-08-12 04:07:39 -050055
56 /* Turn off all secondary CPUs */
57 sunxi_disable_secondary_cpus(plat_my_core_pos());
Samuel Hollandb8566642017-08-12 04:07:39 -050058}
59
60void bl31_plat_arch_setup(void)
61{
62 sunxi_configure_mmu_el3(0);
63}
64
65void bl31_platform_setup(void)
66{
Andre Przywarac2366b92018-06-22 00:47:08 +010067 const char *soc_name;
68 uint16_t soc_id = sunxi_read_soc_id();
69
70 switch (soc_id) {
71 case 0x1689:
72 soc_name = "A64/H64/R18";
73 break;
74 case 0x1718:
75 soc_name = "H5";
76 break;
Andre Przywaraaa26f532017-12-08 01:27:02 +000077 case 0x1728:
78 soc_name = "H6";
79 break;
Andre Przywarac2366b92018-06-22 00:47:08 +010080 default:
81 soc_name = "unknown";
82 break;
83 }
84 NOTICE("BL31: Detected Allwinner %s SoC (%04x)\n", soc_name, soc_id);
85
Samuel Hollandb8566642017-08-12 04:07:39 -050086 generic_delay_timer_init();
87
88 /* Configure the interrupt controller */
89 gicv2_driver_init(&sunxi_gic_data);
90 gicv2_distif_init();
91 gicv2_pcpu_distif_init();
92 gicv2_cpuif_enable();
93
Andre Przywara13815472018-06-01 02:01:39 +010094 sunxi_security_setup();
95
Samuel Hollandb8566642017-08-12 04:07:39 -050096 INFO("BL31: Platform setup done\n");
97}
98
99entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
100{
101 assert(sec_state_is_valid(type) != 0);
Amit Singh Tomar2f372242018-06-20 00:44:50 +0530102
103 if (type == NON_SECURE)
104 return &bl33_image_ep_info;
105
106 if ((type == SECURE) && bl32_image_ep_info.pc)
107 return &bl32_image_ep_info;
Samuel Hollandb8566642017-08-12 04:07:39 -0500108
Amit Singh Tomar2f372242018-06-20 00:44:50 +0530109 return NULL;
Samuel Hollandb8566642017-08-12 04:07:39 -0500110}