Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 1 | /* |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 9 | #include <cortex_ares.h> |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 10 | #include <cpuamu.h> |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 11 | #include <cpu_macros.S> |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 12 | |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 13 | /* -------------------------------------------------- |
| 14 | * Errata Workaround for Cortex-Ares Errata |
| 15 | * This applies to revision r0p0 and r1p0 of Cortex-Ares. |
| 16 | * Inputs: |
| 17 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 18 | * Shall clobber: x0-x17 |
| 19 | * -------------------------------------------------- |
| 20 | */ |
| 21 | func errata_ares_1043202_wa |
| 22 | /* Compare x0 against revision r1p0 */ |
| 23 | mov x17, x30 |
| 24 | bl check_errata_1043202 |
| 25 | cbz x0, 1f |
| 26 | |
| 27 | /* Apply instruction patching sequence */ |
| 28 | ldr x0, =0x0 |
| 29 | msr CPUPSELR_EL3, x0 |
| 30 | ldr x0, =0xF3BF8F2F |
| 31 | msr CPUPOR_EL3, x0 |
| 32 | ldr x0, =0xFFFFFFFF |
| 33 | msr CPUPMR_EL3, x0 |
| 34 | ldr x0, =0x800200071 |
| 35 | msr CPUPCR_EL3, x0 |
| 36 | isb |
| 37 | 1: |
| 38 | ret x17 |
| 39 | endfunc errata_ares_1043202_wa |
| 40 | |
| 41 | func check_errata_1043202 |
| 42 | /* Applies to r0p0 and r1p0 */ |
| 43 | mov x1, #0x10 |
| 44 | b cpu_rev_var_ls |
| 45 | endfunc check_errata_1043202 |
| 46 | |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 47 | func cortex_ares_reset_func |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 48 | mov x19, x30 |
| 49 | bl cpu_get_rev_var |
| 50 | mov x18, x0 |
| 51 | |
| 52 | #if ERRATA_ARES_1043202 |
| 53 | mov x0, x18 |
| 54 | bl errata_ares_1043202_wa |
| 55 | #endif |
| 56 | |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 57 | #if ENABLE_AMU |
| 58 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
| 59 | mrs x0, actlr_el3 |
| 60 | orr x0, x0, #CORTEX_ARES_ACTLR_AMEN_BIT |
| 61 | msr actlr_el3, x0 |
| 62 | isb |
| 63 | |
| 64 | /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ |
| 65 | mrs x0, actlr_el2 |
| 66 | orr x0, x0, #CORTEX_ARES_ACTLR_AMEN_BIT |
| 67 | msr actlr_el2, x0 |
| 68 | isb |
| 69 | |
| 70 | /* Enable group0 counters */ |
| 71 | mov x0, #CORTEX_ARES_AMU_GROUP0_MASK |
| 72 | msr CPUAMCNTENSET_EL0, x0 |
| 73 | isb |
| 74 | #endif |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 75 | ret x19 |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 76 | endfunc cortex_ares_reset_func |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 77 | |
| 78 | /* --------------------------------------------- |
| 79 | * HW will do the cache maintenance while powering down |
| 80 | * --------------------------------------------- |
| 81 | */ |
| 82 | func cortex_ares_core_pwr_dwn |
| 83 | /* --------------------------------------------- |
| 84 | * Enable CPU power down bit in power control register |
| 85 | * --------------------------------------------- |
| 86 | */ |
| 87 | mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 |
| 88 | orr x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK |
| 89 | msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 |
| 90 | isb |
| 91 | ret |
| 92 | endfunc cortex_ares_core_pwr_dwn |
| 93 | |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 94 | #if REPORT_ERRATA |
| 95 | /* |
| 96 | * Errata printing function for Cortex-Ares. Must follow AAPCS. |
| 97 | */ |
| 98 | func cortex_a72_errata_report |
| 99 | stp x8, x30, [sp, #-16]! |
| 100 | |
| 101 | bl cpu_get_rev_var |
| 102 | mov x8, x0 |
| 103 | |
| 104 | /* |
| 105 | * Report all errata. The revision-variant information is passed to |
| 106 | * checking functions of each errata. |
| 107 | */ |
| 108 | report_errata ERRATA_ARES_1043202, cortex_ares, 1043202 |
| 109 | |
| 110 | ldp x8, x30, [sp], #16 |
| 111 | ret |
| 112 | endfunc cortex_a72_errata_report |
| 113 | #endif |
| 114 | |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 115 | /* --------------------------------------------- |
| 116 | * This function provides cortex_ares specific |
| 117 | * register information for crash reporting. |
| 118 | * It needs to return with x6 pointing to |
| 119 | * a list of register names in ascii and |
| 120 | * x8 - x15 having values of registers to be |
| 121 | * reported. |
| 122 | * --------------------------------------------- |
| 123 | */ |
| 124 | .section .rodata.cortex_ares_regs, "aS" |
| 125 | cortex_ares_regs: /* The ascii list of register names to be reported */ |
| 126 | .asciz "cpuectlr_el1", "" |
| 127 | |
| 128 | func cortex_ares_cpu_reg_dump |
| 129 | adr x6, cortex_ares_regs |
| 130 | mrs x8, CORTEX_ARES_CPUECTLR_EL1 |
| 131 | ret |
| 132 | endfunc cortex_ares_cpu_reg_dump |
| 133 | |
| 134 | declare_cpu_ops cortex_ares, CORTEX_ARES_MIDR, \ |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 135 | cortex_ares_reset_func, \ |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 136 | cortex_ares_core_pwr_dwn |