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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01008#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +01009#include <assert.h>
10#include <bl_common.h>
11#include <context.h>
Achin Guptaef7a28c2014-02-01 08:59:56 +000012#include <context_mgmt.h>
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000013#include <errata_report.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010014#include <platform.h>
15#include <stddef.h>
Dan Handley714a0d22014-04-09 13:13:04 +010016#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010017
18/*******************************************************************************
Achin Guptaef7a28c2014-02-01 08:59:56 +000019 * Per cpu non-secure contexts used to program the architectural state prior
20 * return to the normal world.
21 * TODO: Use the memory allocator to set aside memory for the contexts instead
Soby Mathew981487a2015-07-13 14:10:57 +010022 * of relying on platform defined constants.
Achin Guptaef7a28c2014-02-01 08:59:56 +000023 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +010024static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT];
Achin Guptaef7a28c2014-02-01 08:59:56 +000025
Soby Mathew6cdddaf2015-01-07 11:10:22 +000026/******************************************************************************
27 * Define the psci capability variable.
28 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010029unsigned int psci_caps;
Soby Mathew6cdddaf2015-01-07 11:10:22 +000030
Dan Handley60b13e32014-05-14 15:13:16 +010031/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +010032 * Function which initializes the 'psci_non_cpu_pd_nodes' or the
33 * 'psci_cpu_pd_nodes' corresponding to the power level.
Achin Gupta4f6ad662013-10-25 09:08:21 +010034 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010035static void psci_init_pwr_domain_node(unsigned int node_idx,
36 unsigned int parent_idx,
37 unsigned int level)
Achin Gupta4f6ad662013-10-25 09:08:21 +010038{
Soby Mathew981487a2015-07-13 14:10:57 +010039 if (level > PSCI_CPU_PWR_LVL) {
40 psci_non_cpu_pd_nodes[node_idx].level = level;
41 psci_lock_init(psci_non_cpu_pd_nodes, node_idx);
42 psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx;
43 psci_non_cpu_pd_nodes[node_idx].local_state =
44 PLAT_MAX_OFF_STATE;
45 } else {
46 psci_cpu_data_t *svc_cpu_data;
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
Soby Mathew981487a2015-07-13 14:10:57 +010048 psci_cpu_pd_nodes[node_idx].parent_node = parent_idx;
Achin Gupta4f6ad662013-10-25 09:08:21 +010049
Soby Mathew981487a2015-07-13 14:10:57 +010050 /* Initialize with an invalid mpidr */
51 psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR;
Soby Mathew2b697502014-10-02 17:24:19 +010052
Soby Mathew981487a2015-07-13 14:10:57 +010053 svc_cpu_data =
54 &(_cpu_data_by_index(node_idx)->psci_svc_cpu_data);
Soby Mathew2b697502014-10-02 17:24:19 +010055
Soby Mathew981487a2015-07-13 14:10:57 +010056 /* Set the Affinity Info for the cores as OFF */
57 svc_cpu_data->aff_info_state = AFF_STATE_OFF;
Achin Gupta4f6ad662013-10-25 09:08:21 +010058
Soby Mathew981487a2015-07-13 14:10:57 +010059 /* Invalidate the suspend level for the cpu */
Soby Mathew011ca182015-07-29 17:05:03 +010060 svc_cpu_data->target_pwrlvl = PSCI_INVALID_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Soby Mathew981487a2015-07-13 14:10:57 +010062 /* Set the power state to OFF state */
63 svc_cpu_data->local_state = PLAT_MAX_OFF_STATE;
Soby Mathew2b697502014-10-02 17:24:19 +010064
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +000065 psci_flush_dcache_range((uintptr_t)svc_cpu_data,
Soby Mathew981487a2015-07-13 14:10:57 +010066 sizeof(*svc_cpu_data));
Achin Gupta4f6ad662013-10-25 09:08:21 +010067
Soby Mathew981487a2015-07-13 14:10:57 +010068 cm_set_context_by_index(node_idx,
69 (void *) &psci_ns_context[node_idx],
70 NON_SECURE);
71 }
Achin Gupta4f6ad662013-10-25 09:08:21 +010072}
73
74/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +010075 * This functions updates cpu_start_idx and ncpus field for each of the node in
76 * psci_non_cpu_pd_nodes[]. It does so by comparing the parent nodes of each of
77 * the CPUs and check whether they match with the parent of the previous
78 * CPU. The basic assumption for this work is that children of the same parent
79 * are allocated adjacent indices. The platform should ensure this though proper
80 * mapping of the CPUs to indices via plat_core_pos_by_mpidr() and
81 * plat_my_core_pos() APIs.
82 *******************************************************************************/
83static void psci_update_pwrlvl_limits(void)
Achin Gupta0959db52013-12-02 17:33:04 +000084{
Soby Mathew011ca182015-07-29 17:05:03 +010085 int j;
Soby Mathew981487a2015-07-13 14:10:57 +010086 unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0};
Soby Mathew011ca182015-07-29 17:05:03 +010087 unsigned int temp_index[PLAT_MAX_PWR_LVL], cpu_idx;
Achin Gupta0959db52013-12-02 17:33:04 +000088
Soby Mathew981487a2015-07-13 14:10:57 +010089 for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) {
90 psci_get_parent_pwr_domain_nodes(cpu_idx,
91 PLAT_MAX_PWR_LVL,
92 temp_index);
93 for (j = PLAT_MAX_PWR_LVL - 1; j >= 0; j--) {
94 if (temp_index[j] != nodes_idx[j]) {
95 nodes_idx[j] = temp_index[j];
96 psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx
97 = cpu_idx;
Achin Gupta0959db52013-12-02 17:33:04 +000098 }
Soby Mathew981487a2015-07-13 14:10:57 +010099 psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++;
100 }
Achin Gupta0959db52013-12-02 17:33:04 +0000101 }
Achin Gupta0959db52013-12-02 17:33:04 +0000102}
103
104/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100105 * Core routine to populate the power domain tree. The tree descriptor passed by
106 * the platform is populated breadth-first and the first entry in the map
107 * informs the number of root power domains. The parent nodes of the root nodes
108 * will point to an invalid entry(-1).
Achin Gupta4f6ad662013-10-25 09:08:21 +0100109 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100110static void populate_power_domain_tree(const unsigned char *topology)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111{
Soby Mathew981487a2015-07-13 14:10:57 +0100112 unsigned int i, j = 0, num_nodes_at_lvl = 1, num_nodes_at_next_lvl;
113 unsigned int node_index = 0, parent_node_index = 0, num_children;
114 int level = PLAT_MAX_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115
116 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100117 * For each level the inputs are:
118 * - number of nodes at this level in plat_array i.e. num_nodes_at_level
119 * This is the sum of values of nodes at the parent level.
120 * - Index of first entry at this level in the plat_array i.e.
121 * parent_node_index.
122 * - Index of first free entry in psci_non_cpu_pd_nodes[] or
123 * psci_cpu_pd_nodes[] i.e. node_index depending upon the level.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100124 */
Soby Mathew981487a2015-07-13 14:10:57 +0100125 while (level >= PSCI_CPU_PWR_LVL) {
126 num_nodes_at_next_lvl = 0;
Achin Guptaef7a28c2014-02-01 08:59:56 +0000127 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100128 * For each entry (parent node) at this level in the plat_array:
129 * - Find the number of children
130 * - Allocate a node in a power domain array for each child
131 * - Set the parent of the child to the parent_node_index - 1
132 * - Increment parent_node_index to point to the next parent
133 * - Accumulate the number of children at next level.
Achin Guptaef7a28c2014-02-01 08:59:56 +0000134 */
Soby Mathew981487a2015-07-13 14:10:57 +0100135 for (i = 0; i < num_nodes_at_lvl; i++) {
136 assert(parent_node_index <=
137 PSCI_NUM_NON_CPU_PWR_DOMAINS);
138 num_children = topology[parent_node_index];
Achin Guptaef7a28c2014-02-01 08:59:56 +0000139
Soby Mathew981487a2015-07-13 14:10:57 +0100140 for (j = node_index;
141 j < node_index + num_children; j++)
142 psci_init_pwr_domain_node(j,
143 parent_node_index - 1,
144 level);
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100145
Soby Mathew981487a2015-07-13 14:10:57 +0100146 node_index = j;
147 num_nodes_at_next_lvl += num_children;
148 parent_node_index++;
149 }
Achin Guptaf6b9e992014-07-31 11:19:11 +0100150
Soby Mathew981487a2015-07-13 14:10:57 +0100151 num_nodes_at_lvl = num_nodes_at_next_lvl;
152 level--;
Soby Mathew7d861ea2014-11-18 10:14:14 +0000153
Soby Mathew981487a2015-07-13 14:10:57 +0100154 /* Reset the index for the cpu power domain array */
155 if (level == PSCI_CPU_PWR_LVL)
156 node_index = 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100157 }
158
Soby Mathew981487a2015-07-13 14:10:57 +0100159 /* Validate the sanity of array exported by the platform */
160 assert(j == PLATFORM_CORE_COUNT);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100161}
162
163/*******************************************************************************
Soby Mathewd0194872016-04-29 19:01:30 +0100164 * This function does the architectural setup and takes the warm boot
165 * entry-point `mailbox_ep` as an argument. The function also initializes the
166 * power domain topology tree by querying the platform. The power domain nodes
167 * higher than the CPU are populated in the array psci_non_cpu_pd_nodes[] and
168 * the CPU power domains are populated in psci_cpu_pd_nodes[]. The platform
169 * exports its static topology map through the
Soby Mathew981487a2015-07-13 14:10:57 +0100170 * populate_power_domain_topology_tree() API. The algorithm populates the
171 * psci_non_cpu_pd_nodes and psci_cpu_pd_nodes iteratively by using this
Soby Mathewd0194872016-04-29 19:01:30 +0100172 * topology map. On a platform that implements two clusters of 2 cpus each,
173 * and supporting 3 domain levels, the populated psci_non_cpu_pd_nodes would
174 * look like this:
Achin Gupta4f6ad662013-10-25 09:08:21 +0100175 *
Achin Gupta4f6ad662013-10-25 09:08:21 +0100176 * ---------------------------------------------------
Soby Mathew981487a2015-07-13 14:10:57 +0100177 * | system node | cluster 0 node | cluster 1 node |
Achin Gupta4f6ad662013-10-25 09:08:21 +0100178 * ---------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100179 *
Soby Mathew981487a2015-07-13 14:10:57 +0100180 * And populated psci_cpu_pd_nodes would look like this :
181 * <- cpus cluster0 -><- cpus cluster1 ->
182 * ------------------------------------------------
183 * | CPU 0 | CPU 1 | CPU 2 | CPU 3 |
184 * ------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100185 ******************************************************************************/
Soby Mathew89256b82016-09-13 14:19:08 +0100186int psci_setup(const psci_lib_args_t *lib_args)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100187{
Soby Mathew981487a2015-07-13 14:10:57 +0100188 const unsigned char *topology_tree;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100189
Soby Mathew89256b82016-09-13 14:19:08 +0100190 assert(VERIFY_PSCI_LIB_ARGS_V1(lib_args));
191
Soby Mathewd0194872016-04-29 19:01:30 +0100192 /* Do the Architectural initialization */
193 psci_arch_setup();
194
Soby Mathew981487a2015-07-13 14:10:57 +0100195 /* Query the topology map from the platform */
196 topology_tree = plat_get_power_domain_tree_desc();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197
Soby Mathew981487a2015-07-13 14:10:57 +0100198 /* Populate the power domain arrays using the platform topology map */
199 populate_power_domain_tree(topology_tree);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200
Soby Mathew981487a2015-07-13 14:10:57 +0100201 /* Update the CPU limits for each node in psci_non_cpu_pd_nodes */
202 psci_update_pwrlvl_limits();
203
204 /* Populate the mpidr field of cpu node for this CPU */
205 psci_cpu_pd_nodes[plat_my_core_pos()].mpidr =
206 read_mpidr() & MPIDR_AFFINITY_MASK;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100207
Soby Mathew981487a2015-07-13 14:10:57 +0100208 psci_init_req_local_pwr_states();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100209
210 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100211 * Set the requested and target state of this CPU and all the higher
212 * power domain levels for this CPU to run.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100213 */
Soby Mathew981487a2015-07-13 14:10:57 +0100214 psci_set_pwr_domains_to_run(PLAT_MAX_PWR_LVL);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100215
Soby Mathew89256b82016-09-13 14:19:08 +0100216 plat_setup_psci_ops((uintptr_t)lib_args->mailbox_ep, &psci_plat_pm_ops);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217 assert(psci_plat_pm_ops);
218
Soby Mathew7c9d5f82016-09-09 11:33:58 +0100219 /*
220 * Flush `psci_plat_pm_ops` as it will be accessed by secondary CPUs
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000221 * during warm boot, possibly before data cache is enabled.
Soby Mathew7c9d5f82016-09-09 11:33:58 +0100222 */
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000223 psci_flush_dcache_range((uintptr_t)&psci_plat_pm_ops,
Soby Mathew7c9d5f82016-09-09 11:33:58 +0100224 sizeof(psci_plat_pm_ops));
225
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000226 /* Initialize the psci capability */
227 psci_caps = PSCI_GENERIC_CAP;
228
Soby Mathew981487a2015-07-13 14:10:57 +0100229 if (psci_plat_pm_ops->pwr_domain_off)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000230 psci_caps |= define_psci_cap(PSCI_CPU_OFF);
Soby Mathew981487a2015-07-13 14:10:57 +0100231 if (psci_plat_pm_ops->pwr_domain_on &&
232 psci_plat_pm_ops->pwr_domain_on_finish)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000233 psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64);
Soby Mathew981487a2015-07-13 14:10:57 +0100234 if (psci_plat_pm_ops->pwr_domain_suspend &&
235 psci_plat_pm_ops->pwr_domain_suspend_finish) {
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000236 psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64);
Soby Mathew96168382014-12-17 14:47:57 +0000237 if (psci_plat_pm_ops->get_sys_suspend_power_state)
238 psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64);
239 }
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000240 if (psci_plat_pm_ops->system_off)
241 psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF);
242 if (psci_plat_pm_ops->system_reset)
243 psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET);
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100244 if (psci_plat_pm_ops->get_node_hw_state)
245 psci_caps |= define_psci_cap(PSCI_NODE_HW_STATE_AARCH64);
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100246 if (psci_plat_pm_ops->read_mem_protect &&
247 psci_plat_pm_ops->write_mem_protect)
248 psci_caps |= define_psci_cap(PSCI_MEM_PROTECT);
249 if (psci_plat_pm_ops->mem_protect_chk)
250 psci_caps |= define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64);
Roberto Vargasb820ad02017-07-26 09:23:09 +0100251 if (psci_plat_pm_ops->system_reset2)
252 psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64);
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000253
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100254#if ENABLE_PSCI_STAT
255 psci_caps |= define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64);
256 psci_caps |= define_psci_cap(PSCI_STAT_COUNT_AARCH64);
257#endif
258
Achin Gupta7421b462014-02-01 18:53:26 +0000259 return 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100260}
Soby Mathewd0194872016-04-29 19:01:30 +0100261
262/*******************************************************************************
263 * This duplicates what the primary cpu did after a cold boot in BL1. The same
264 * needs to be done when a cpu is hotplugged in. This function could also over-
265 * ride any EL3 setup done by BL1 as this code resides in rw memory.
266 ******************************************************************************/
267void psci_arch_setup(void)
268{
269 /* Program the counter frequency */
270 write_cntfrq_el0(plat_get_syscnt_freq2());
271
272 /* Initialize the cpu_ops pointer. */
273 init_cpu_ops();
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +0000274
275 /* Having initialized cpu_ops, we can now print errata status */
276 print_errata_status();
Soby Mathewd0194872016-04-29 19:01:30 +0100277}
Soby Mathew89d90dc2016-05-05 14:11:23 +0100278
279/******************************************************************************
280 * PSCI Library interface to initialize the cpu context for the next non
281 * secure image during cold boot. The relevant registers in the cpu context
282 * need to be retrieved and programmed on return from this interface.
283 *****************************************************************************/
284void psci_prepare_next_non_secure_ctx(entry_point_info_t *next_image_info)
285{
286 assert(GET_SECURITY_STATE(next_image_info->h.attr) == NON_SECURE);
287 cm_init_my_context(next_image_info);
288 cm_prepare_el3_exit(NON_SECURE);
289}