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Samuel Hollandb8566642017-08-12 04:07:39 -05001/*
Samuel Hollandcd120442021-01-16 01:21:38 -06002 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
Samuel Hollandb8566642017-08-12 04:07:39 -05003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Samuel Hollandb8566642017-08-12 04:07:39 -05007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Samuel Hollandb8566642017-08-12 04:07:39 -05009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <arch_helpers.h>
12#include <common/debug.h>
Samuel Holland103ee9b2018-10-21 12:41:03 -050013#include <drivers/arm/css/css_scpi.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <drivers/arm/gicv2.h>
15#include <drivers/delay_timer.h>
16#include <lib/mmio.h>
17#include <lib/psci/psci.h>
18#include <plat/common/platform.h>
19
Samuel Holland0a9018c2017-08-12 04:07:39 -050020#include <sunxi_cpucfg.h>
Samuel Holland103ee9b2018-10-21 12:41:03 -050021#include <sunxi_def.h>
Andre Przywara456208a2018-10-14 12:02:02 +010022#include <sunxi_mmap.h>
23#include <sunxi_private.h>
Samuel Hollandb8566642017-08-12 04:07:39 -050024
Clément Péron3071a1f2019-04-09 00:15:06 +020025#define SUNXI_WDOG0_CTRL_REG (SUNXI_R_WDOG_BASE + 0x0010)
26#define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014)
27#define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018)
Samuel Hollandb8566642017-08-12 04:07:39 -050028
Samuel Holland103ee9b2018-10-21 12:41:03 -050029#define CPU_PWR_LVL MPIDR_AFFLVL0
30#define CLUSTER_PWR_LVL MPIDR_AFFLVL1
31#define SYSTEM_PWR_LVL MPIDR_AFFLVL2
32
33#define CPU_PWR_STATE(state) \
34 ((state)->pwr_domain_state[CPU_PWR_LVL])
35#define CLUSTER_PWR_STATE(state) \
36 ((state)->pwr_domain_state[CLUSTER_PWR_LVL])
37#define SYSTEM_PWR_STATE(state) \
38 ((state)->pwr_domain_state[SYSTEM_PWR_LVL])
39
Samuel Holland103ee9b2018-10-21 12:41:03 -050040/*
41 * The addresses for the SCP exception vectors are defined in the or1k
42 * architecture specification.
43 */
44#define OR1K_VEC_FIRST 0x01
45#define OR1K_VEC_LAST 0x0e
46#define OR1K_VEC_ADDR(n) (0x100 * (n))
47
48/*
49 * This magic value is the little-endian representation of the or1k
50 * instruction "l.mfspr r2, r0, 0x12", which is guaranteed to be the
51 * first instruction in the SCP firmware.
52 */
53#define SCP_FIRMWARE_MAGIC 0xb4400012
54
55static bool scpi_available;
56
57static inline scpi_power_state_t scpi_map_state(plat_local_state_t psci_state)
58{
59 if (is_local_state_run(psci_state))
60 return scpi_power_on;
61 if (is_local_state_retn(psci_state))
62 return scpi_power_retention;
63 return scpi_power_off;
64}
65
66static void sunxi_cpu_standby(plat_local_state_t cpu_state)
67{
68 u_register_t scr = read_scr_el3();
69
70 assert(is_local_state_retn(cpu_state));
71
72 write_scr_el3(scr | SCR_IRQ_BIT);
73 wfi();
74 write_scr_el3(scr);
75}
Samuel Holland0a9018c2017-08-12 04:07:39 -050076
77static int sunxi_pwr_domain_on(u_register_t mpidr)
78{
Samuel Holland103ee9b2018-10-21 12:41:03 -050079 if (scpi_available) {
80 scpi_set_css_power_state(mpidr,
81 scpi_power_on,
82 scpi_power_on,
83 scpi_power_on);
84 } else {
85 sunxi_cpu_on(mpidr);
86 }
Samuel Holland0a9018c2017-08-12 04:07:39 -050087
88 return PSCI_E_SUCCESS;
89}
90
91static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
92{
Samuel Holland103ee9b2018-10-21 12:41:03 -050093 plat_local_state_t cpu_pwr_state = CPU_PWR_STATE(target_state);
94 plat_local_state_t cluster_pwr_state = CLUSTER_PWR_STATE(target_state);
95 plat_local_state_t system_pwr_state = SYSTEM_PWR_STATE(target_state);
96
97 if (is_local_state_off(cpu_pwr_state))
98 gicv2_cpuif_disable();
99
100 if (scpi_available) {
101 scpi_set_css_power_state(read_mpidr(),
102 scpi_map_state(cpu_pwr_state),
103 scpi_map_state(cluster_pwr_state),
104 scpi_map_state(system_pwr_state));
105 }
Samuel Holland0a9018c2017-08-12 04:07:39 -0500106}
107
Andre Przywara6d0b81b2018-09-28 00:43:32 +0100108static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state)
109{
Samuel Hollandc629daf2019-02-17 15:33:33 -0600110 sunxi_cpu_off(read_mpidr());
Andre Przywara6d0b81b2018-09-28 00:43:32 +0100111
112 while (1)
113 wfi();
114}
115
Samuel Holland0a9018c2017-08-12 04:07:39 -0500116static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
117{
Samuel Holland103ee9b2018-10-21 12:41:03 -0500118 if (is_local_state_off(SYSTEM_PWR_STATE(target_state)))
119 gicv2_distif_init();
120 if (is_local_state_off(CPU_PWR_STATE(target_state))) {
121 gicv2_pcpu_distif_init();
122 gicv2_cpuif_enable();
123 }
Samuel Holland0a9018c2017-08-12 04:07:39 -0500124}
125
Samuel Hollandb8566642017-08-12 04:07:39 -0500126static void __dead2 sunxi_system_off(void)
127{
Samuel Holland103ee9b2018-10-21 12:41:03 -0500128 gicv2_cpuif_disable();
129
130 if (scpi_available) {
131 /* Send the power down request to the SCP */
132 uint32_t ret = scpi_sys_power_state(scpi_system_shutdown);
133
134 if (ret != SCP_OK)
135 ERROR("PSCI: SCPI %s failed: %d\n", "shutdown", ret);
136 }
137
Samuel Holland321c0ab2017-08-12 04:07:39 -0500138 /* Turn off all secondary CPUs */
Samuel Hollandc629daf2019-02-17 15:33:33 -0600139 sunxi_disable_secondary_cpus(read_mpidr());
Samuel Holland321c0ab2017-08-12 04:07:39 -0500140
Icenowy Zhengbd57eb52018-07-22 21:52:50 +0800141 sunxi_power_down();
Samuel Hollandfa4d9352019-10-20 15:06:57 -0500142
143 udelay(1000);
144 ERROR("PSCI: Cannot turn off system, halting\n");
145 wfi();
146 panic();
Samuel Hollandb8566642017-08-12 04:07:39 -0500147}
148
149static void __dead2 sunxi_system_reset(void)
150{
Samuel Holland103ee9b2018-10-21 12:41:03 -0500151 gicv2_cpuif_disable();
152
153 if (scpi_available) {
154 /* Send the system reset request to the SCP */
155 uint32_t ret = scpi_sys_power_state(scpi_system_reboot);
156
157 if (ret != SCP_OK)
158 ERROR("PSCI: SCPI %s failed: %d\n", "reboot", ret);
159 }
160
Samuel Hollandb8566642017-08-12 04:07:39 -0500161 /* Reset the whole system when the watchdog times out */
162 mmio_write_32(SUNXI_WDOG0_CFG_REG, 1);
163 /* Enable the watchdog with the shortest timeout (0.5 seconds) */
164 mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1);
165 /* Wait for twice the watchdog timeout before panicking */
166 mdelay(1000);
167
168 ERROR("PSCI: System reset failed\n");
169 wfi();
170 panic();
171}
172
Samuel Holland103ee9b2018-10-21 12:41:03 -0500173static int sunxi_validate_power_state(unsigned int power_state,
174 psci_power_state_t *req_state)
175{
176 unsigned int power_level = psci_get_pstate_pwrlvl(power_state);
177 unsigned int type = psci_get_pstate_type(power_state);
178
179 assert(req_state != NULL);
180
181 if (power_level > PLAT_MAX_PWR_LVL)
182 return PSCI_E_INVALID_PARAMS;
183
184 if (type == PSTATE_TYPE_STANDBY) {
185 /* Only one retention power state is supported. */
186 if (psci_get_pstate_id(power_state) > 0)
187 return PSCI_E_INVALID_PARAMS;
188 /* The SoC cannot be suspended without losing state */
189 if (power_level == SYSTEM_PWR_LVL)
190 return PSCI_E_INVALID_PARAMS;
191 for (unsigned int i = 0; i <= power_level; ++i)
192 req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE;
193 } else {
194 /* Only one off power state is supported. */
195 if (psci_get_pstate_id(power_state) > 0)
196 return PSCI_E_INVALID_PARAMS;
197 for (unsigned int i = 0; i <= power_level; ++i)
198 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
199 }
200 /* Higher power domain levels should all remain running */
201 for (unsigned int i = power_level + 1; i <= PLAT_MAX_PWR_LVL; ++i)
202 req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN;
203
204 return PSCI_E_SUCCESS;
205}
206
Samuel Holland0a9018c2017-08-12 04:07:39 -0500207static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
208{
209 /* The non-secure entry point must be in DRAM */
Samuel Hollandcd120442021-01-16 01:21:38 -0600210 if (ns_entrypoint < SUNXI_DRAM_BASE) {
211 return PSCI_E_INVALID_ADDRESS;
212 }
Samuel Holland0a9018c2017-08-12 04:07:39 -0500213
Samuel Hollandcd120442021-01-16 01:21:38 -0600214 return PSCI_E_SUCCESS;
Samuel Holland0a9018c2017-08-12 04:07:39 -0500215}
216
Samuel Holland103ee9b2018-10-21 12:41:03 -0500217static void sunxi_get_sys_suspend_power_state(psci_power_state_t *req_state)
218{
219 assert(req_state);
220
221 for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i)
222 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
223}
224
Samuel Hollandb8566642017-08-12 04:07:39 -0500225static plat_psci_ops_t sunxi_psci_ops = {
Samuel Holland103ee9b2018-10-21 12:41:03 -0500226 .cpu_standby = sunxi_cpu_standby,
Samuel Holland0a9018c2017-08-12 04:07:39 -0500227 .pwr_domain_on = sunxi_pwr_domain_on,
228 .pwr_domain_off = sunxi_pwr_domain_off,
229 .pwr_domain_on_finish = sunxi_pwr_domain_on_finish,
Samuel Hollandb8566642017-08-12 04:07:39 -0500230 .system_off = sunxi_system_off,
231 .system_reset = sunxi_system_reset,
Samuel Holland103ee9b2018-10-21 12:41:03 -0500232 .validate_power_state = sunxi_validate_power_state,
Samuel Holland0a9018c2017-08-12 04:07:39 -0500233 .validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
Samuel Hollandb8566642017-08-12 04:07:39 -0500234};
235
236int plat_setup_psci_ops(uintptr_t sec_entrypoint,
237 const plat_psci_ops_t **psci_ops)
238{
239 assert(psci_ops);
240
Samuel Holland103ee9b2018-10-21 12:41:03 -0500241 /* Program all CPU entry points. */
242 for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; ++cpu) {
Samuel Holland0a9018c2017-08-12 04:07:39 -0500243 mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu),
244 sec_entrypoint & 0xffffffff);
245 mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu),
246 sec_entrypoint >> 32);
247 }
248
Samuel Holland103ee9b2018-10-21 12:41:03 -0500249 /* Check for a valid SCP firmware, and boot the SCP if found. */
250 if (mmio_read_32(SUNXI_SCP_BASE) == SCP_FIRMWARE_MAGIC) {
251 /* Program SCP exception vectors to the firmware entrypoint. */
252 for (unsigned int i = OR1K_VEC_FIRST; i <= OR1K_VEC_LAST; ++i) {
253 uint32_t vector = SUNXI_SRAM_A2_BASE + OR1K_VEC_ADDR(i);
254 uint32_t offset = SUNXI_SCP_BASE - vector;
255
256 mmio_write_32(vector, offset >> 2);
257 clean_dcache_range(vector, sizeof(uint32_t));
258 }
259 /* Take the SCP out of reset. */
260 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
261 /* Wait for the SCP firmware to boot. */
262 if (scpi_wait_ready() == 0)
263 scpi_available = true;
264 }
265
266 NOTICE("PSCI: System suspend is %s\n",
267 scpi_available ? "available via SCPI" : "unavailable");
268 if (scpi_available) {
269 /* Suspend is only available via SCPI. */
270 sunxi_psci_ops.pwr_domain_suspend = sunxi_pwr_domain_off;
271 sunxi_psci_ops.pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish;
272 sunxi_psci_ops.get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state;
Samuel Holland103ee9b2018-10-21 12:41:03 -0500273 } else {
274 /* This is only needed when SCPI is unavailable. */
275 sunxi_psci_ops.pwr_domain_pwr_down_wfi = sunxi_pwr_down_wfi;
276 }
277
Samuel Hollandb8566642017-08-12 04:07:39 -0500278 *psci_ops = &sunxi_psci_ops;
279
280 return 0;
281}