Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
Varun Wadekar | a64806a | 2016-01-05 15:17:41 -0800 | [diff] [blame] | 33 | #include <assert.h> |
| 34 | #include <bl_common.h> |
| 35 | #include <context.h> |
| 36 | #include <context_mgmt.h> |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 37 | #include <debug.h> |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 38 | #include <denver.h> |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 39 | #include <mce.h> |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 40 | #include <platform.h> |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 41 | #include <psci.h> |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 42 | #include <smmu.h> |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 43 | #include <string.h> |
Varun Wadekar | 782c83d | 2017-03-14 14:25:35 -0700 | [diff] [blame] | 44 | #include <t18x_ari.h> |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 45 | #include <tegra_private.h> |
| 46 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 47 | extern void prepare_cpu_pwr_dwn(void); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 48 | extern void tegra186_cpu_reset_handler(void); |
| 49 | extern uint32_t __tegra186_cpu_reset_handler_data, |
| 50 | __tegra186_cpu_reset_handler_end; |
| 51 | |
| 52 | /* TZDRAM offset for saving SMMU context */ |
| 53 | #define TEGRA186_SMMU_CTX_OFFSET 16 |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 54 | |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 55 | /* state id mask */ |
| 56 | #define TEGRA186_STATE_ID_MASK 0xF |
| 57 | /* constants to get power state's wake time */ |
Krishna Sitaraman | 86569d1 | 2016-08-18 15:41:21 -0700 | [diff] [blame] | 58 | #define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0 |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 59 | #define TEGRA186_WAKE_TIME_SHIFT 4 |
Varun Wadekar | 698e7c6 | 2016-03-28 15:05:03 -0700 | [diff] [blame] | 60 | /* default core wake mask for CPU_SUSPEND */ |
| 61 | #define TEGRA186_CORE_WAKE_MASK 0x180c |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 62 | /* context size to save during system suspend */ |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 63 | #define TEGRA186_SE_CONTEXT_SIZE 3 |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 64 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 65 | static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; |
Mustafa Yigit Bilgen | f40bc2c | 2016-09-02 19:30:22 -0700 | [diff] [blame] | 66 | static struct t18x_psci_percpu_data { |
| 67 | unsigned int wake_time; |
| 68 | } __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT]; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 69 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 70 | /* System power down state */ |
| 71 | uint32_t tegra186_system_powerdn_state = TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF; |
| 72 | |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 73 | int32_t tegra_soc_validate_power_state(unsigned int power_state, |
| 74 | psci_power_state_t *req_state) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 75 | { |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 76 | int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 77 | int cpu = plat_my_core_pos(); |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 78 | |
Krishna Sitaraman | 86569d1 | 2016-08-18 15:41:21 -0700 | [diff] [blame] | 79 | /* save the core wake time (in TSC ticks)*/ |
| 80 | percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) |
| 81 | << TEGRA186_WAKE_TIME_SHIFT; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 82 | |
Mustafa Yigit Bilgen | f40bc2c | 2016-09-02 19:30:22 -0700 | [diff] [blame] | 83 | /* |
| 84 | * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that |
| 85 | * the correct value is read in tegra_soc_pwr_domain_suspend(), which |
| 86 | * is called with caches disabled. It is possible to read a stale value |
| 87 | * from DRAM in that function, because the L2 cache is not flushed |
| 88 | * unless the cluster is entering CC6/CC7. |
| 89 | */ |
| 90 | clean_dcache_range((uint64_t)&percpu_data[cpu], |
| 91 | sizeof(percpu_data[cpu])); |
| 92 | |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 93 | /* Sanity check the requested state id */ |
| 94 | switch (state_id) { |
| 95 | case PSTATE_ID_CORE_IDLE: |
| 96 | case PSTATE_ID_CORE_POWERDN: |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 97 | |
| 98 | /* Core powerdown request */ |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 99 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 100 | req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 101 | |
| 102 | break; |
| 103 | |
| 104 | default: |
| 105 | ERROR("%s: unsupported state id (%d)\n", __func__, state_id); |
| 106 | return PSCI_E_INVALID_PARAMS; |
| 107 | } |
| 108 | |
| 109 | return PSCI_E_SUCCESS; |
| 110 | } |
| 111 | |
| 112 | int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
| 113 | { |
| 114 | const plat_local_state_t *pwr_domain_state; |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 115 | unsigned int stateid_afflvl0, stateid_afflvl2; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 116 | int cpu = plat_my_core_pos(); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 117 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 118 | mce_cstate_info_t cstate_info = { 0 }; |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 119 | uint64_t smmu_ctx_base; |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 120 | uint32_t val; |
| 121 | |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 122 | /* get the state ID */ |
| 123 | pwr_domain_state = target_state->pwr_domain_state; |
| 124 | stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & |
| 125 | TEGRA186_STATE_ID_MASK; |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 126 | stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & |
| 127 | TEGRA186_STATE_ID_MASK; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 128 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 129 | if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) || |
| 130 | (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 131 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 132 | /* Enter CPU idle/powerdown */ |
| 133 | val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? |
| 134 | TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7; |
| 135 | (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val, |
Mustafa Yigit Bilgen | f40bc2c | 2016-09-02 19:30:22 -0700 | [diff] [blame] | 136 | percpu_data[cpu].wake_time, 0); |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 137 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 138 | } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 139 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 140 | /* save SE registers */ |
| 141 | se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + |
| 142 | SE_MUTEX_WATCHDOG_NS_LIMIT); |
| 143 | se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE + |
| 144 | RNG_MUTEX_WATCHDOG_NS_LIMIT); |
| 145 | se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE + |
| 146 | PKA_MUTEX_WATCHDOG_NS_LIMIT); |
| 147 | |
| 148 | /* save 'Secure Boot' Processor Feature Config Register */ |
| 149 | val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); |
| 150 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val); |
| 151 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 152 | /* save SMMU context to TZDRAM */ |
| 153 | smmu_ctx_base = params_from_bl2->tzdram_base + |
| 154 | ((uintptr_t)&__tegra186_cpu_reset_handler_data - |
| 155 | (uintptr_t)tegra186_cpu_reset_handler) + |
| 156 | TEGRA186_SMMU_CTX_OFFSET; |
| 157 | tegra_smmu_save_context((uintptr_t)smmu_ctx_base); |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 158 | |
| 159 | /* Prepare for system suspend */ |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 160 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; |
| 161 | cstate_info.system = TEGRA_ARI_SYSTEM_SC7; |
| 162 | cstate_info.system_state_force = 1; |
| 163 | cstate_info.update_wake_mask = 1; |
| 164 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 165 | |
Varun Wadekar | a9002bb | 2016-03-28 15:11:43 -0700 | [diff] [blame] | 166 | /* Loop until system suspend is allowed */ |
| 167 | do { |
| 168 | val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, |
| 169 | TEGRA_ARI_CORE_C7, |
| 170 | MCE_CORE_SLEEP_TIME_INFINITE, |
| 171 | 0); |
| 172 | } while (val == 0); |
| 173 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 174 | /* Instruct the MCE to enter system suspend state */ |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 175 | (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, |
| 176 | TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | return PSCI_E_SUCCESS; |
| 180 | } |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 181 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 182 | /******************************************************************************* |
| 183 | * Platform handler to calculate the proper target power level at the |
| 184 | * specified affinity level |
| 185 | ******************************************************************************/ |
| 186 | plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, |
| 187 | const plat_local_state_t *states, |
| 188 | unsigned int ncpu) |
| 189 | { |
| 190 | plat_local_state_t target = *states; |
| 191 | int cpu = plat_my_core_pos(), ret, cluster_powerdn = 1; |
| 192 | int core_pos = read_mpidr() & MPIDR_CPU_MASK; |
| 193 | mce_cstate_info_t cstate_info = { 0 }; |
| 194 | |
| 195 | /* get the current core's power state */ |
| 196 | target = *(states + core_pos); |
| 197 | |
| 198 | /* CPU suspend */ |
| 199 | if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) { |
| 200 | |
| 201 | /* Program default wake mask */ |
| 202 | cstate_info.wake_mask = TEGRA186_CORE_WAKE_MASK; |
| 203 | cstate_info.update_wake_mask = 1; |
| 204 | mce_update_cstate_info(&cstate_info); |
| 205 | |
| 206 | /* Check if CCx state is allowed. */ |
| 207 | ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, |
Mustafa Yigit Bilgen | f40bc2c | 2016-09-02 19:30:22 -0700 | [diff] [blame] | 208 | TEGRA_ARI_CORE_C7, percpu_data[cpu].wake_time, |
| 209 | 0); |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 210 | if (ret) |
| 211 | return PSTATE_ID_CORE_POWERDN; |
| 212 | } |
| 213 | |
| 214 | /* CPU off */ |
| 215 | if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) { |
| 216 | |
| 217 | /* find out the number of ON cpus in the cluster */ |
| 218 | do { |
| 219 | target = *states++; |
| 220 | if (target != PLAT_MAX_OFF_STATE) |
| 221 | cluster_powerdn = 0; |
| 222 | } while (--ncpu); |
| 223 | |
| 224 | /* Enable cluster powerdn from last CPU in the cluster */ |
| 225 | if (cluster_powerdn) { |
| 226 | |
| 227 | /* Enable CC7 state and turn off wake mask */ |
| 228 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; |
| 229 | cstate_info.update_wake_mask = 1; |
| 230 | mce_update_cstate_info(&cstate_info); |
| 231 | |
| 232 | /* Check if CCx state is allowed. */ |
| 233 | ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, |
| 234 | TEGRA_ARI_CORE_C7, |
| 235 | MCE_CORE_SLEEP_TIME_INFINITE, |
| 236 | 0); |
| 237 | if (ret) |
| 238 | return PSTATE_ID_CORE_POWERDN; |
| 239 | |
| 240 | } else { |
| 241 | |
| 242 | /* Turn off wake_mask */ |
| 243 | cstate_info.update_wake_mask = 1; |
| 244 | mce_update_cstate_info(&cstate_info); |
| 245 | } |
| 246 | } |
| 247 | |
| 248 | /* System Suspend */ |
| 249 | if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN)) |
| 250 | return PSTATE_ID_SOC_POWERDN; |
| 251 | |
| 252 | /* default state */ |
| 253 | return PSCI_LOCAL_STATE_RUN; |
| 254 | } |
| 255 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 256 | int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) |
| 257 | { |
| 258 | const plat_local_state_t *pwr_domain_state = |
| 259 | target_state->pwr_domain_state; |
| 260 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
| 261 | unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & |
| 262 | TEGRA186_STATE_ID_MASK; |
| 263 | uint32_t val; |
| 264 | |
| 265 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 266 | /* |
| 267 | * The TZRAM loses power when we enter system suspend. To |
| 268 | * allow graceful exit from system suspend, we need to copy |
| 269 | * BL3-1 over to TZDRAM. |
| 270 | */ |
| 271 | val = params_from_bl2->tzdram_base + |
| 272 | ((uintptr_t)&__tegra186_cpu_reset_handler_end - |
| 273 | (uintptr_t)tegra186_cpu_reset_handler); |
| 274 | memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, |
| 275 | (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); |
| 276 | } |
| 277 | |
| 278 | return PSCI_E_SUCCESS; |
| 279 | } |
| 280 | |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 281 | int tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 282 | { |
| 283 | int target_cpu = mpidr & MPIDR_CPU_MASK; |
| 284 | int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> |
| 285 | MPIDR_AFFINITY_BITS; |
| 286 | |
| 287 | if (target_cluster > MPIDR_AFFLVL1) { |
| 288 | ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); |
| 289 | return PSCI_E_NOT_PRESENT; |
| 290 | } |
| 291 | |
| 292 | /* construct the target CPU # */ |
| 293 | target_cpu |= (target_cluster << 2); |
| 294 | |
| 295 | mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); |
| 296 | |
| 297 | return PSCI_E_SUCCESS; |
| 298 | } |
| 299 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 300 | int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
| 301 | { |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 302 | int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; |
| 303 | int stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0]; |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 304 | mce_cstate_info_t cstate_info = { 0 }; |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 305 | |
| 306 | /* |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 307 | * Reset power state info for CPUs when onlining, we set |
| 308 | * deepest power when offlining a core but that may not be |
| 309 | * requested by non-secure sw which controls idle states. It |
| 310 | * will re-init this info from non-secure software when the |
| 311 | * core come online. |
Varun Wadekar | d2da47a | 2016-04-09 00:40:45 -0700 | [diff] [blame] | 312 | */ |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 313 | if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) { |
| 314 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 315 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC1; |
| 316 | cstate_info.update_wake_mask = 1; |
| 317 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 318 | } |
Varun Wadekar | d2da47a | 2016-04-09 00:40:45 -0700 | [diff] [blame] | 319 | |
| 320 | /* |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 321 | * Check if we are exiting from deep sleep and restore SE |
| 322 | * context if we are. |
| 323 | */ |
Varun Wadekar | 5a40256 | 2016-04-29 11:25:46 -0700 | [diff] [blame] | 324 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 325 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 326 | mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT, |
| 327 | se_regs[0]); |
| 328 | mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT, |
| 329 | se_regs[1]); |
| 330 | mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT, |
| 331 | se_regs[2]); |
| 332 | |
| 333 | /* Init SMMU */ |
| 334 | tegra_smmu_init(); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 335 | |
| 336 | /* |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 337 | * Reset power state info for the last core doing SC7 |
| 338 | * entry and exit, we set deepest power state as CC7 |
| 339 | * and SC7 for SC7 entry which may not be requested by |
| 340 | * non-secure SW which controls idle states. |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 341 | */ |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 342 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; |
| 343 | cstate_info.system = TEGRA_ARI_SYSTEM_SC1; |
| 344 | cstate_info.update_wake_mask = 1; |
| 345 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | return PSCI_E_SUCCESS; |
| 349 | } |
| 350 | |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 351 | int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 352 | { |
Varun Wadekar | e26a55a | 2016-02-26 11:09:21 -0800 | [diff] [blame] | 353 | int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
Varun Wadekar | a64806a | 2016-01-05 15:17:41 -0800 | [diff] [blame] | 354 | |
Varun Wadekar | e26a55a | 2016-02-26 11:09:21 -0800 | [diff] [blame] | 355 | /* Disable Denver's DCO operations */ |
| 356 | if (impl == DENVER_IMPL) |
| 357 | denver_disable_dco(); |
| 358 | |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 359 | /* Turn off CPU */ |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 360 | (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 361 | MCE_CORE_SLEEP_TIME_INFINITE, 0); |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 362 | |
| 363 | return PSCI_E_SUCCESS; |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 364 | } |
Varun Wadekar | 782c83d | 2017-03-14 14:25:35 -0700 | [diff] [blame] | 365 | |
| 366 | __dead2 void tegra_soc_prepare_system_off(void) |
| 367 | { |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 368 | mce_cstate_info_t cstate_info = { 0 }; |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 369 | uint32_t val; |
| 370 | |
| 371 | if (tegra186_system_powerdn_state == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) { |
| 372 | |
| 373 | /* power off the entire system */ |
| 374 | mce_enter_ccplex_state(tegra186_system_powerdn_state); |
| 375 | |
| 376 | } else if (tegra186_system_powerdn_state == TEGRA_ARI_SYSTEM_SC8) { |
| 377 | |
Varun Wadekar | a9002bb | 2016-03-28 15:11:43 -0700 | [diff] [blame] | 378 | /* Prepare for quasi power down */ |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 379 | cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; |
| 380 | cstate_info.system = TEGRA_ARI_SYSTEM_SC8; |
| 381 | cstate_info.system_state_force = 1; |
| 382 | cstate_info.update_wake_mask = 1; |
| 383 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | a9002bb | 2016-03-28 15:11:43 -0700 | [diff] [blame] | 384 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 385 | /* loop until other CPUs power down */ |
| 386 | do { |
| 387 | val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, |
| 388 | TEGRA_ARI_CORE_C7, |
| 389 | MCE_CORE_SLEEP_TIME_INFINITE, |
| 390 | 0); |
| 391 | } while (val == 0); |
| 392 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 393 | /* Enter quasi power down state */ |
| 394 | (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, |
| 395 | TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); |
| 396 | |
| 397 | /* disable GICC */ |
| 398 | tegra_gic_cpuif_deactivate(); |
| 399 | |
| 400 | /* power down core */ |
| 401 | prepare_cpu_pwr_dwn(); |
| 402 | |
Varun Wadekar | 4a0b37a | 2016-04-09 00:36:42 -0700 | [diff] [blame] | 403 | /* flush L1/L2 data caches */ |
| 404 | dcsw_op_all(DCCISW); |
| 405 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 406 | } else { |
| 407 | ERROR("%s: unsupported power down state (%d)\n", __func__, |
| 408 | tegra186_system_powerdn_state); |
| 409 | } |
| 410 | |
| 411 | wfi(); |
| 412 | |
| 413 | /* wait for the system to power down */ |
| 414 | for (;;) { |
| 415 | ; |
| 416 | } |
Varun Wadekar | 782c83d | 2017-03-14 14:25:35 -0700 | [diff] [blame] | 417 | } |
Varun Wadekar | 38020c9 | 2016-01-07 14:36:12 -0800 | [diff] [blame] | 418 | |
| 419 | int tegra_soc_prepare_system_reset(void) |
| 420 | { |
| 421 | mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT); |
| 422 | |
| 423 | return PSCI_E_SUCCESS; |
| 424 | } |