Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 1 | /* |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 2 | * Copyright (c) 2019-2020, ARM Limited. All rights reserved. |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 10 | #include <cortex_a78_ae.h> |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 16 | #error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled" |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 17 | #endif |
| 18 | |
| 19 | /* ------------------------------------------------- |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 20 | * The CPU Ops reset function for Cortex-A78-AE |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 21 | * ------------------------------------------------- |
| 22 | */ |
| 23 | #if ENABLE_AMU |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 24 | func cortex_a78_ae_reset_func |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 25 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
| 26 | mrs x0, actlr_el3 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 27 | bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 28 | msr actlr_el3, x0 |
| 29 | |
| 30 | /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ |
| 31 | mrs x0, actlr_el2 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 32 | bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 33 | msr actlr_el2, x0 |
| 34 | |
| 35 | /* Enable group0 counters */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 36 | mov x0, #CORTEX_A78_AMU_GROUP0_MASK |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 37 | msr CPUAMCNTENSET0_EL0, x0 |
| 38 | |
| 39 | /* Enable group1 counters */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 40 | mov x0, #CORTEX_A78_AMU_GROUP1_MASK |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 41 | msr CPUAMCNTENSET1_EL0, x0 |
| 42 | isb |
| 43 | |
| 44 | ret |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 45 | endfunc cortex_a78_ae_reset_func |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 46 | #endif |
| 47 | |
| 48 | /* ------------------------------------------------------- |
| 49 | * HW will do the cache maintenance while powering down |
| 50 | * ------------------------------------------------------- |
| 51 | */ |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 52 | func cortex_a78_ae_core_pwr_dwn |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 53 | /* ------------------------------------------------------- |
| 54 | * Enable CPU power down bit in power control register |
| 55 | * ------------------------------------------------------- |
| 56 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 57 | mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 |
| 58 | orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT |
| 59 | msr CORTEX_A78_CPUPWRCTLR_EL1, x0 |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 60 | isb |
| 61 | ret |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 62 | endfunc cortex_a78_ae_core_pwr_dwn |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 63 | |
| 64 | /* |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 65 | * Errata printing function for cortex_a78_ae. Must follow AAPCS. |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 66 | */ |
| 67 | #if REPORT_ERRATA |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 68 | func cortex_a78_ae_errata_report |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 69 | ret |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 70 | endfunc cortex_a78_ae_errata_report |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 71 | #endif |
| 72 | |
| 73 | /* ------------------------------------------------------- |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 74 | * This function provides cortex_a78_ae specific |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 75 | * register information for crash reporting. |
| 76 | * It needs to return with x6 pointing to |
| 77 | * a list of register names in ascii and |
| 78 | * x8 - x15 having values of registers to be |
| 79 | * reported. |
| 80 | * ------------------------------------------------------- |
| 81 | */ |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 82 | .section .rodata.cortex_a78_ae_regs, "aS" |
| 83 | cortex_a78_ae_regs: /* The ascii list of register names to be reported */ |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 84 | .asciz "cpuectlr_el1", "" |
| 85 | |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 86 | func cortex_a78_ae_cpu_reg_dump |
| 87 | adr x6, cortex_a78_ae_regs |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 88 | mrs x8, CORTEX_A78_CPUECTLR_EL1 |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 89 | ret |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 90 | endfunc cortex_a78_ae_cpu_reg_dump |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 91 | |
| 92 | #if ENABLE_AMU |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 93 | #define A78_AE_RESET_FUNC cortex_a78_ae_reset_func |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 94 | #else |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 95 | #define A78_AE_RESET_FUNC CPU_NO_RESET_FUNC |
Artsem Artsemenka | fea97f7 | 2019-09-16 15:11:21 +0100 | [diff] [blame] | 96 | #endif |
| 97 | |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 98 | declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \ |
| 99 | A78_AE_RESET_FUNC, \ |
| 100 | cortex_a78_ae_core_pwr_dwn |