Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 30 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 31 | #include <asm_macros.S> |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 32 | #include <bl_common.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 33 | #include <cortex_a53.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 34 | #include <cpu_macros.S> |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 35 | #include <debug.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 36 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 37 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 38 | #if A53_DISABLE_NON_TEMPORAL_HINT |
| 39 | #undef ERRATA_A53_836870 |
| 40 | #define ERRATA_A53_836870 1 |
| 41 | #endif |
| 42 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 43 | /* --------------------------------------------- |
| 44 | * Disable L1 data cache and unified L2 cache |
| 45 | * --------------------------------------------- |
| 46 | */ |
| 47 | func cortex_a53_disable_dcache |
| 48 | mrs x1, sctlr_el3 |
| 49 | bic x1, x1, #SCTLR_C_BIT |
| 50 | msr sctlr_el3, x1 |
| 51 | isb |
| 52 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 53 | endfunc cortex_a53_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 54 | |
| 55 | /* --------------------------------------------- |
| 56 | * Disable intra-cluster coherency |
| 57 | * --------------------------------------------- |
| 58 | */ |
| 59 | func cortex_a53_disable_smp |
| 60 | mrs x0, CPUECTLR_EL1 |
| 61 | bic x0, x0, #CPUECTLR_SMP_BIT |
| 62 | msr CPUECTLR_EL1, x0 |
| 63 | isb |
| 64 | dsb sy |
| 65 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 66 | endfunc cortex_a53_disable_smp |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 67 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 68 | /* -------------------------------------------------- |
| 69 | * Errata Workaround for Cortex A53 Errata #826319. |
| 70 | * This applies only to revision <= r0p2 of Cortex A53. |
| 71 | * Inputs: |
| 72 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 73 | * Shall clobber: x0-x17 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 74 | * -------------------------------------------------- |
| 75 | */ |
| 76 | func errata_a53_826319_wa |
| 77 | /* |
| 78 | * Compare x0 against revision r0p2 |
| 79 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 80 | mov x17, x30 |
| 81 | bl check_errata_826319 |
| 82 | cbz x0, 1f |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 83 | mrs x1, L2ACTLR_EL1 |
| 84 | bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN |
| 85 | orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH |
| 86 | msr L2ACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 87 | 1: |
| 88 | ret x17 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 89 | endfunc errata_a53_826319_wa |
| 90 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 91 | func check_errata_826319 |
| 92 | mov x1, #0x02 |
| 93 | b cpu_rev_var_ls |
| 94 | endfunc check_errata_826319 |
| 95 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 96 | /* --------------------------------------------------------------------- |
| 97 | * Disable the cache non-temporal hint. |
| 98 | * |
| 99 | * This ignores the Transient allocation hint in the MAIR and treats |
| 100 | * allocations the same as non-transient allocation types. As a result, |
| 101 | * the LDNP and STNP instructions in AArch64 behave the same as the |
| 102 | * equivalent LDP and STP instructions. |
| 103 | * |
| 104 | * This is relevant only for revisions <= r0p3 of Cortex-A53. |
| 105 | * From r0p4 and onwards, the bit to disable the hint is enabled by |
| 106 | * default at reset. |
| 107 | * |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 108 | * Inputs: |
| 109 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 110 | * Shall clobber: x0-x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 111 | * --------------------------------------------------------------------- |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 112 | */ |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 113 | func a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 114 | /* |
| 115 | * Compare x0 against revision r0p3 |
| 116 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 117 | mov x17, x30 |
| 118 | bl check_errata_disable_non_temporal_hint |
| 119 | cbz x0, 1f |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 120 | mrs x1, CPUACTLR_EL1 |
| 121 | orr x1, x1, #CPUACTLR_DTAH |
| 122 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 123 | 1: |
| 124 | ret x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 125 | endfunc a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 126 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 127 | func check_errata_disable_non_temporal_hint |
| 128 | mov x1, #0x03 |
| 129 | b cpu_rev_var_ls |
| 130 | endfunc check_errata_disable_non_temporal_hint |
| 131 | |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 132 | /* -------------------------------------------------- |
| 133 | * Errata Workaround for Cortex A53 Errata #855873. |
| 134 | * |
| 135 | * This applies only to revisions >= r0p3 of Cortex A53. |
| 136 | * Earlier revisions of the core are affected as well, but don't |
| 137 | * have the chicken bit in the CPUACTLR register. It is expected that |
| 138 | * the rich OS takes care of that, especially as the workaround is |
| 139 | * shared with other erratas in those revisions of the CPU. |
| 140 | * Inputs: |
| 141 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 142 | * Shall clobber: x0-x17 |
| 143 | * -------------------------------------------------- |
| 144 | */ |
| 145 | func errata_a53_855873_wa |
| 146 | /* |
| 147 | * Compare x0 against revision r0p3 and higher |
| 148 | */ |
| 149 | mov x17, x30 |
| 150 | bl check_errata_855873 |
| 151 | cbz x0, 1f |
| 152 | |
| 153 | mrs x1, CPUACTLR_EL1 |
| 154 | orr x1, x1, #CPUACTLR_ENDCCASCI |
| 155 | msr CPUACTLR_EL1, x1 |
| 156 | 1: |
| 157 | ret x17 |
| 158 | endfunc errata_a53_855873_wa |
| 159 | |
| 160 | func check_errata_855873 |
| 161 | mov x1, #0x03 |
| 162 | b cpu_rev_var_hs |
| 163 | endfunc check_errata_855873 |
| 164 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 165 | /* ------------------------------------------------- |
| 166 | * The CPU Ops reset function for Cortex-A53. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 167 | * Shall clobber: x0-x19 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 168 | * ------------------------------------------------- |
| 169 | */ |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 170 | func cortex_a53_reset_func |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 171 | mov x19, x30 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 172 | bl cpu_get_rev_var |
| 173 | mov x18, x0 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 174 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 175 | |
| 176 | #if ERRATA_A53_826319 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 177 | mov x0, x18 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 178 | bl errata_a53_826319_wa |
| 179 | #endif |
| 180 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 181 | #if ERRATA_A53_836870 |
| 182 | mov x0, x18 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 183 | bl a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 184 | #endif |
| 185 | |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 186 | #if ERRATA_A53_855873 |
| 187 | mov x0, x18 |
| 188 | bl errata_a53_855873_wa |
| 189 | #endif |
| 190 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 191 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 192 | * Enable the SMP bit. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 193 | * --------------------------------------------- |
| 194 | */ |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 195 | mrs x0, CPUECTLR_EL1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 196 | orr x0, x0, #CPUECTLR_SMP_BIT |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 197 | msr CPUECTLR_EL1, x0 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 198 | isb |
| 199 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 200 | endfunc cortex_a53_reset_func |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 201 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 202 | func cortex_a53_core_pwr_dwn |
| 203 | mov x18, x30 |
| 204 | |
| 205 | /* --------------------------------------------- |
| 206 | * Turn off caches. |
| 207 | * --------------------------------------------- |
| 208 | */ |
| 209 | bl cortex_a53_disable_dcache |
| 210 | |
| 211 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 212 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 213 | * --------------------------------------------- |
| 214 | */ |
| 215 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 216 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 217 | |
| 218 | /* --------------------------------------------- |
| 219 | * Come out of intra cluster coherency |
| 220 | * --------------------------------------------- |
| 221 | */ |
| 222 | mov x30, x18 |
| 223 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 224 | endfunc cortex_a53_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 225 | |
| 226 | func cortex_a53_cluster_pwr_dwn |
| 227 | mov x18, x30 |
| 228 | |
| 229 | /* --------------------------------------------- |
| 230 | * Turn off caches. |
| 231 | * --------------------------------------------- |
| 232 | */ |
| 233 | bl cortex_a53_disable_dcache |
| 234 | |
| 235 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 236 | * Flush L1 caches. |
| 237 | * --------------------------------------------- |
| 238 | */ |
| 239 | mov x0, #DCCISW |
| 240 | bl dcsw_op_level1 |
| 241 | |
| 242 | /* --------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 243 | * Disable the optional ACP. |
| 244 | * --------------------------------------------- |
| 245 | */ |
| 246 | bl plat_disable_acp |
| 247 | |
| 248 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 249 | * Flush L2 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 250 | * --------------------------------------------- |
| 251 | */ |
| 252 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 253 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 254 | |
| 255 | /* --------------------------------------------- |
| 256 | * Come out of intra cluster coherency |
| 257 | * --------------------------------------------- |
| 258 | */ |
| 259 | mov x30, x18 |
| 260 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 261 | endfunc cortex_a53_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 262 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 263 | #if REPORT_ERRATA |
| 264 | /* |
| 265 | * Errata printing function for Cortex A53. Must follow AAPCS. |
| 266 | */ |
| 267 | func cortex_a53_errata_report |
| 268 | stp x8, x30, [sp, #-16]! |
| 269 | |
| 270 | bl cpu_get_rev_var |
| 271 | mov x8, x0 |
| 272 | |
| 273 | /* |
| 274 | * Report all errata. The revision-variant information is passed to |
| 275 | * checking functions of each errata. |
| 276 | */ |
| 277 | report_errata ERRATA_A53_826319, cortex_a53, 826319 |
| 278 | report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 279 | report_errata ERRATA_A53_855873, cortex_a53, 855873 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 280 | |
| 281 | ldp x8, x30, [sp], #16 |
| 282 | ret |
| 283 | endfunc cortex_a53_errata_report |
| 284 | #endif |
| 285 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 286 | /* --------------------------------------------- |
| 287 | * This function provides cortex_a53 specific |
| 288 | * register information for crash reporting. |
| 289 | * It needs to return with x6 pointing to |
| 290 | * a list of register names in ascii and |
| 291 | * x8 - x15 having values of registers to be |
| 292 | * reported. |
| 293 | * --------------------------------------------- |
| 294 | */ |
| 295 | .section .rodata.cortex_a53_regs, "aS" |
| 296 | cortex_a53_regs: /* The ascii list of register names to be reported */ |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 297 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ |
| 298 | "cpuactlr_el1", "" |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 299 | |
| 300 | func cortex_a53_cpu_reg_dump |
| 301 | adr x6, cortex_a53_regs |
| 302 | mrs x8, CPUECTLR_EL1 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 303 | mrs x9, CPUMERRSR_EL1 |
| 304 | mrs x10, L2MERRSR_EL1 |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 305 | mrs x11, CPUACTLR_EL1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 306 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 307 | endfunc cortex_a53_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 308 | |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 309 | declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ |
| 310 | cortex_a53_reset_func, \ |
| 311 | cortex_a53_core_pwr_dwn, \ |
| 312 | cortex_a53_cluster_pwr_dwn |