| Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 1 | /* |
| Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 2 | * Copyright (c) 2019-2022, ARM Limited. All rights reserved. |
| Varun Wadekar | 0914fc4 | 2021-07-27 02:32:29 -0700 | [diff] [blame] | 3 | * Copyright (c) 2021, NVIDIA Corporation. All rights reserved. |
| Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef CORTEX_A78_AE_H |
| 9 | #define CORTEX_A78_AE_H |
| 10 | |
| 11 | #include <cortex_a78.h> |
| 12 | |
| Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 13 | #define CORTEX_A78_AE_MIDR U(0x410FD420) |
| 14 | |
| 15 | /* Cortex-A78AE loop count for CVE-2022-23960 mitigation */ |
| 16 | #define CORTEX_A78_AE_BHB_LOOP_COUNT U(32) |
| Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 17 | |
| Varun Wadekar | 0914fc4 | 2021-07-27 02:32:29 -0700 | [diff] [blame] | 18 | /******************************************************************************* |
| 19 | * CPU Extended Control register specific definitions. |
| 20 | ******************************************************************************/ |
| 21 | #define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1 |
| 22 | #define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8 |
| 23 | |
| Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 24 | #endif /* CORTEX_A78_AE_H */ |