Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <lib/mmio.h> |
| 9 | |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 10 | #include <tegra_def.h> |
| 11 | #include <tegra_platform.h> |
| 12 | #include <tegra_private.h> |
| 13 | |
| 14 | /******************************************************************************* |
| 15 | * Tegra platforms |
| 16 | ******************************************************************************/ |
| 17 | typedef enum tegra_platform { |
| 18 | TEGRA_PLATFORM_SILICON = 0, |
| 19 | TEGRA_PLATFORM_QT, |
| 20 | TEGRA_PLATFORM_FPGA, |
| 21 | TEGRA_PLATFORM_EMULATION, |
| 22 | TEGRA_PLATFORM_MAX, |
| 23 | } tegra_platform_t; |
| 24 | |
| 25 | /******************************************************************************* |
| 26 | * Tegra macros defining all the SoC minor versions |
| 27 | ******************************************************************************/ |
| 28 | #define TEGRA_MINOR_QT 0 |
| 29 | #define TEGRA_MINOR_FPGA 1 |
| 30 | #define TEGRA_MINOR_EMULATION_MIN 2 |
| 31 | #define TEGRA_MINOR_EMULATION_MAX 10 |
| 32 | |
| 33 | /******************************************************************************* |
| 34 | * Tegra major, minor version helper macros |
| 35 | ******************************************************************************/ |
| 36 | #define MAJOR_VERSION_SHIFT 0x4 |
| 37 | #define MAJOR_VERSION_MASK 0xF |
| 38 | #define MINOR_VERSION_SHIFT 0x10 |
| 39 | #define MINOR_VERSION_MASK 0xF |
| 40 | #define CHIP_ID_SHIFT 8 |
| 41 | #define CHIP_ID_MASK 0xFF |
| 42 | |
| 43 | /******************************************************************************* |
| 44 | * Tegra chip ID values |
| 45 | ******************************************************************************/ |
| 46 | typedef enum tegra_chipid { |
| 47 | TEGRA_CHIPID_TEGRA13 = 0x13, |
| 48 | TEGRA_CHIPID_TEGRA21 = 0x21, |
Varun Wadekar | fdcdfe2 | 2017-04-13 14:12:49 -0700 | [diff] [blame] | 49 | TEGRA_CHIPID_TEGRA18 = 0x18, |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 50 | } tegra_chipid_t; |
| 51 | |
| 52 | /* |
| 53 | * Read the chip ID value |
| 54 | */ |
| 55 | static uint32_t tegra_get_chipid(void) |
| 56 | { |
| 57 | return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); |
| 58 | } |
| 59 | |
| 60 | /* |
| 61 | * Read the chip's major version from chip ID value |
| 62 | */ |
Varun Wadekar | fc9b91e | 2017-03-10 09:53:37 -0800 | [diff] [blame] | 63 | uint32_t tegra_get_chipid_major(void) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 64 | { |
| 65 | return (tegra_get_chipid() >> MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; |
| 66 | } |
| 67 | |
| 68 | /* |
| 69 | * Read the chip's minor version from the chip ID value |
| 70 | */ |
Varun Wadekar | fc9b91e | 2017-03-10 09:53:37 -0800 | [diff] [blame] | 71 | uint32_t tegra_get_chipid_minor(void) |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 72 | { |
| 73 | return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; |
| 74 | } |
| 75 | |
| 76 | uint8_t tegra_chipid_is_t132(void) |
| 77 | { |
| 78 | uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; |
| 79 | |
| 80 | return (chip_id == TEGRA_CHIPID_TEGRA13); |
| 81 | } |
| 82 | |
| 83 | uint8_t tegra_chipid_is_t210(void) |
| 84 | { |
| 85 | uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; |
| 86 | |
| 87 | return (chip_id == TEGRA_CHIPID_TEGRA21); |
| 88 | } |
| 89 | |
Varun Wadekar | fdcdfe2 | 2017-04-13 14:12:49 -0700 | [diff] [blame] | 90 | uint8_t tegra_chipid_is_t186(void) |
| 91 | { |
| 92 | uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; |
| 93 | |
| 94 | return (chip_id == TEGRA_CHIPID_TEGRA18); |
| 95 | } |
| 96 | |
Varun Wadekar | 28dcc21 | 2016-07-20 10:28:51 -0700 | [diff] [blame] | 97 | /* |
| 98 | * Read the chip ID value and derive the platform |
| 99 | */ |
| 100 | static tegra_platform_t tegra_get_platform(void) |
| 101 | { |
| 102 | uint32_t major = tegra_get_chipid_major(); |
| 103 | uint32_t minor = tegra_get_chipid_minor(); |
| 104 | |
| 105 | /* Actual silicon platforms have a non-zero major version */ |
| 106 | if (major > 0) |
| 107 | return TEGRA_PLATFORM_SILICON; |
| 108 | |
| 109 | /* |
| 110 | * The minor version number is used by simulation platforms |
| 111 | */ |
| 112 | |
| 113 | /* |
| 114 | * Cadence's QuickTurn emulation system is a Solaris-based |
| 115 | * chip emulation system |
| 116 | */ |
| 117 | if (minor == TEGRA_MINOR_QT) |
| 118 | return TEGRA_PLATFORM_QT; |
| 119 | |
| 120 | /* |
| 121 | * FPGAs are used during early software/hardware development |
| 122 | */ |
| 123 | if (minor == TEGRA_MINOR_FPGA) |
| 124 | return TEGRA_PLATFORM_FPGA; |
| 125 | |
| 126 | /* Minor version reserved for other emulation platforms */ |
| 127 | if ((minor > TEGRA_MINOR_FPGA) && (minor <= TEGRA_MINOR_EMULATION_MAX)) |
| 128 | return TEGRA_PLATFORM_EMULATION; |
| 129 | |
| 130 | /* unsupported platform */ |
| 131 | return TEGRA_PLATFORM_MAX; |
| 132 | } |
| 133 | |
| 134 | uint8_t tegra_platform_is_silicon(void) |
| 135 | { |
| 136 | return (tegra_get_platform() == TEGRA_PLATFORM_SILICON); |
| 137 | } |
| 138 | |
| 139 | uint8_t tegra_platform_is_qt(void) |
| 140 | { |
| 141 | return (tegra_get_platform() == TEGRA_PLATFORM_QT); |
| 142 | } |
| 143 | |
| 144 | uint8_t tegra_platform_is_fpga(void) |
| 145 | { |
| 146 | return (tegra_get_platform() == TEGRA_PLATFORM_FPGA); |
| 147 | } |
| 148 | |
| 149 | uint8_t tegra_platform_is_emulation(void) |
| 150 | { |
| 151 | return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION); |
| 152 | } |