blob: 50c6c0aa674643f3783355987dfe2e7dec056788 [file] [log] [blame]
Stephan Gerhold4bc53a12022-08-28 15:18:55 +02001/*
2 * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net>
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.h>
8#include <drivers/console.h>
9#include <drivers/generic_delay_timer.h>
10#include <lib/mmio.h>
11#include <lib/xlat_tables/xlat_mmu_helpers.h>
12#include <lib/xlat_tables/xlat_tables_v2.h>
13
14#include "msm8916_gicv2.h"
15#include <msm8916_mmap.h>
16#include "msm8916_setup.h"
17#include <uartdm_console.h>
18
19static const mmap_region_t msm8916_mmap[] = {
20 MAP_REGION_FLAT(PCNOC_BASE, PCNOC_SIZE,
21 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
22 MAP_REGION_FLAT(APCS_BASE, APCS_SIZE,
23 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
24 {},
25};
26
27static console_t console;
28
29unsigned int plat_get_syscnt_freq2(void)
30{
31 return PLAT_SYSCNT_FREQ;
32}
33
34#define GPIO_BLSP_UART2_TX 4
35#define GPIO_BLSP_UART2_RX 5
36#define GPIO_CFG_FUNC_BLSP_UART2 (U(0x2) << 2)
37#define GPIO_CFG_DRV_STRENGTH_16MA (U(0x7) << 6)
38
39#define CLK_ENABLE BIT_32(0)
40#define CLK_OFF BIT_32(31)
41#define GCC_BLSP1_AHB_CBCR (GCC_BASE + 0x01008)
42#define GCC_BLSP1_UART2_APPS_CBCR (GCC_BASE + 0x0302c)
43#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x45004)
44#define BLSP1_AHB_CLK_ENA BIT_32(10)
45
46/*
47 * The previous boot stage seems to disable most of the UART setup before exit
48 * so it must be enabled here again before the UART console can be used.
49 */
50static void msm8916_enable_blsp_uart2(void)
51{
52 /* Route GPIOs to BLSP UART2 */
53 mmio_write_32(TLMM_GPIO_CFG(GPIO_BLSP_UART2_TX),
54 GPIO_CFG_FUNC_BLSP_UART2 | GPIO_CFG_DRV_STRENGTH_16MA);
55 mmio_write_32(TLMM_GPIO_CFG(GPIO_BLSP_UART2_RX),
56 GPIO_CFG_FUNC_BLSP_UART2 | GPIO_CFG_DRV_STRENGTH_16MA);
57
58 /* Enable AHB clock */
59 mmio_setbits_32(GCC_APCS_CLOCK_BRANCH_ENA_VOTE, BLSP1_AHB_CLK_ENA);
60 while (mmio_read_32(GCC_BLSP1_AHB_CBCR) & CLK_OFF)
61 ;
62
63 /* Enable BLSP UART2 clock */
64 mmio_setbits_32(GCC_BLSP1_UART2_APPS_CBCR, CLK_ENABLE);
65 while (mmio_read_32(GCC_BLSP1_UART2_APPS_CBCR) & CLK_OFF)
66 ;
67}
68
69void msm8916_early_platform_setup(void)
70{
71 /* Initialize the debug console as early as possible */
72 msm8916_enable_blsp_uart2();
73 console_uartdm_register(&console, BLSP_UART2_BASE);
74}
75
76void msm8916_plat_arch_setup(uintptr_t base, size_t size)
77{
78 mmap_add_region(base, base, size, MT_RW_DATA | MT_SECURE);
79 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
80 BL_CODE_END - BL_CODE_BASE,
81 MT_CODE | MT_SECURE);
82 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
83 BL_RO_DATA_END - BL_RO_DATA_BASE,
84 MT_RO_DATA | MT_SECURE);
85 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
86 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
87 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
88
89 mmap_add(msm8916_mmap);
90 init_xlat_tables();
91}
92
93void msm8916_platform_setup(void)
94{
95 generic_delay_timer_init();
96 msm8916_gicv2_init();
97}