Sandrine Bailleux | 1fe4336 | 2014-07-17 09:56:29 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <bl_common.h> |
| 32 | #include <console.h> |
| 33 | #include <platform_tsp.h> |
| 34 | #include "../juno_def.h" |
| 35 | #include "../juno_private.h" |
| 36 | |
| 37 | /******************************************************************************* |
| 38 | * Declarations of linker defined symbols which will help us find the layout |
| 39 | * of trusted SRAM |
| 40 | ******************************************************************************/ |
| 41 | extern unsigned long __RO_START__; |
| 42 | extern unsigned long __RO_END__; |
| 43 | |
| 44 | extern unsigned long __COHERENT_RAM_START__; |
| 45 | extern unsigned long __COHERENT_RAM_END__; |
| 46 | |
| 47 | /* |
| 48 | * The next 2 constants identify the extents of the code & RO data region. |
| 49 | * These addresses are used by the MMU setup code and therefore they must be |
| 50 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 51 | * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. |
| 52 | */ |
| 53 | #define BL32_RO_BASE (unsigned long)(&__RO_START__) |
| 54 | #define BL32_RO_LIMIT (unsigned long)(&__RO_END__) |
| 55 | |
| 56 | /* |
| 57 | * The next 2 constants identify the extents of the coherent memory region. |
| 58 | * These addresses are used by the MMU setup code and therefore they must be |
| 59 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 60 | * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to |
| 61 | * page-aligned addresses. |
| 62 | */ |
| 63 | #define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) |
| 64 | #define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) |
| 65 | |
| 66 | /******************************************************************************* |
| 67 | * Initialize the UART |
| 68 | ******************************************************************************/ |
| 69 | void tsp_early_platform_setup(void) |
| 70 | { |
| 71 | /* |
| 72 | * Initialize a different console than already in use to display |
| 73 | * messages from TSP |
| 74 | */ |
Soby Mathew | f797cea | 2014-08-21 15:20:27 +0100 | [diff] [blame] | 75 | console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); |
Sandrine Bailleux | 1fe4336 | 2014-07-17 09:56:29 +0100 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | /******************************************************************************* |
| 79 | * Perform platform specific setup placeholder |
| 80 | ******************************************************************************/ |
| 81 | void tsp_platform_setup(void) |
| 82 | { |
Juan Castillo | b3286c0 | 2014-10-20 12:29:58 +0100 | [diff] [blame] | 83 | plat_gic_init(); |
Sandrine Bailleux | 1fe4336 | 2014-07-17 09:56:29 +0100 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | /******************************************************************************* |
| 87 | * Perform the very early platform specific architectural setup here. At the |
| 88 | * moment this only intializes the MMU |
| 89 | ******************************************************************************/ |
| 90 | void tsp_plat_arch_setup(void) |
| 91 | { |
| 92 | configure_mmu_el1(BL32_RO_BASE, |
| 93 | BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE, |
| 94 | BL32_RO_BASE, |
| 95 | BL32_RO_LIMIT, |
| 96 | BL32_COHERENT_RAM_BASE, |
| 97 | BL32_COHERENT_RAM_LIMIT); |
| 98 | } |